JP2589876B2 - 半導体集積回路装置 - Google Patents

半導体集積回路装置

Info

Publication number
JP2589876B2
JP2589876B2 JP2403096A JP40309690A JP2589876B2 JP 2589876 B2 JP2589876 B2 JP 2589876B2 JP 2403096 A JP2403096 A JP 2403096A JP 40309690 A JP40309690 A JP 40309690A JP 2589876 B2 JP2589876 B2 JP 2589876B2
Authority
JP
Japan
Prior art keywords
terminal
measured
resistance
integrated circuit
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2403096A
Other languages
English (en)
Other versions
JPH04217341A (ja
Inventor
忠義 清家
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
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Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP2403096A priority Critical patent/JP2589876B2/ja
Publication of JPH04217341A publication Critical patent/JPH04217341A/ja
Application granted granted Critical
Publication of JP2589876B2 publication Critical patent/JP2589876B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は、半導体集積回路装置と
くに端子抵抗測定の可能なものに関するものである。
【０００２】
【従来の技術】図３は従来のボンディングワイヤと半導
体チップの接続の検査をする半導体集積回路装置の１例
を示すものである。図３において、２５は半導体チッ
プ、２６はＮ型半導体基板、２７はＮ型半導体基板の上
に形成されたＰ型半導体、２８はシリコンの酸化膜、２
９は中間絶縁膜、３０は金属配線、３１は表面保護膜、
３２はボンディングパッド、３３はボンディングワイ
ヤ、３４はインナーリード、３５は電源である。
【０００３】このように構成された従来の半導体集積回
路装置について以下その動作を説明する。Ｎ型基板２６
をＧＮＤレベルにし、インナーリード３４に電源３５よ
り負の電位を与える。３４は３２のボンディングパッド
を介し、金属配線３０を通ってＰ型半導体２７と接続さ
れる。Ｎ型半導体基板２６とＰ型半導体２７はＰＮ接合
の順方向となっているので、順方向の電位差がある一定
以上になると２６から２７の方向へ電流が流れる。この
電流はボンディングワイヤ，リード線を通って外へ流れ
出す。ＰＮ接合の順方向に一定電圧がかかるようにし、
電流が流れるかどうかで、ボンディングワイヤと半導体
チップの接続が正常に行なわれているかどうか検査する
ことができる。
【０００４】
【発明が解決しようとする課題】しかしながら、上記の
従来の構成では、ＰＮ接合の順方向に電流が流れるかど
うかでのワイヤボンディングの検査であったので、ワイ
ヤボンディング接触抵抗（以下ボンディング抵抗と呼
ぶ）の測定，検査ができないとういう問題点を有してい
た。
【０００５】本発明は上記従来の問題点を解決するもの
で、ボンディング接触抵抗の測定のできる半導体集積回
路装置を提供することを目的とする。
【０００６】
【課題を解決するための手段】この目的を達成するため
に、本発明の半導体集積回路装置は、被測定端子とチッ
プ内部にこれにアナログスイッチを介して接続する２個
の測定端子を設け、その１個の測定端子より電流を流
し、他の測定端子より電圧を測定できるように構成した
ものである。
【０００７】
【作用】この構成によって、被測定端子のボンディング
抵抗測定時に、外部からアナログスイッチの制御電極に
制御信号を印加して２個のアナログスイッチを閉状態に
して２個の測定端子をそれぞれ被測定端子と接続する。
さらに１個の測定端子から被測定端子に電流を流し、そ
のときのボンディング抵抗による電圧低下を他の測定端
子を用いて測定して、ボンディング抵抗を正確に測定す
ることが可能である。
【０００８】
【実施例】以下、本発明の一実施例について、図面を参
照しながら説明する。
【０００９】図１は本発明の一実施例における半導体集
積回路装置を示すものである。図１において、１は第１
の測定端子のインナーリード１Ａを有し、２は第２の測
定端子でのインナーリード２Ａを有し、３は被測定端子
でインナーリード３Ａを有し、４は第１の測定端子のボ
ンディングワイヤ、５は第２の測定端子のボンディング
ワイヤ、６は被測定端子のボンディングワイヤ、７は第
１の測定端子のボンディングパッド、８は第２の測定端
子のボンディングパッド、９は被測定端子のボンディン
グパッド、１０および１１はＮチャンネル型ＭＯＳトラ
ンジスタよりなるアナログスイッチ、１２は第１の回
路、１３は第２の回路、１４は半導体チップである。た
だし、第１の回路および第２の回路とは、この半導体チ
ップの回路を構成する一部の回路である。
【００１０】以上のように構成された半導体集積回路装
置について以下にボンディング抵抗の測定方法を説明す
る。ＮチャンネルＭＯＳトランジスタ１０と１１のゲー
トには、端子抵抗測定時、ハイレベルの電圧が印加され
ともにオン状態にある。また１０と１１は被測定端子の
ボンディングパッド９にそれぞれ接続されている。第１
の測定端子のインナーリードと被測定端子のインナーリ
ード間に電圧計を接続する。また第２の測定端子のイン
ナーリードと被測定端子のインナーリード間に電源およ
び電流計を接続する。端子抵抗測定時には、第１の測定
端子からはトランジスタ１０にのみ、第２の測定端子か
らトランジスタ１１にのみ電流が流れるように状態が固
定されており、またこのとき第１の回路、第２の回路か
らは被測定端子に電流が流れないよう外部からの電圧印
加操作により状態が固定されている。図２は図１を等価
回路にした端子抵抗の測定回路である。図２において１
５は測定端子１の端子抵抗、１６は測定端子２の端子抵
抗、１７は被測定端子の端子抵抗、１８，２０はそれぞ
れアナログスイッチ１０をスイッチとオン抵抗に置き直
したもの、１９，２１はそれぞれアナログスイッチ１１
をスイッチとオン抵抗に置き直したものである。２２は
電圧計、２３は電流計である。２４は外部配線抵抗であ
る。
【００１１】第２の測定端子から電流Ｉを流したとき、
第１の測定端子の電圧をＶとする。Ｖは被測定端子の端
子抵抗Ｒと外部配線抵抗２４の抵抗値ｒの両端の電位差
である。従ってＶ＝Ｉ（Ｒ＋ｒ）となる。外部配線抵抗
ｒをＲに比べて無視できる大きさにすることによってＶ
≒ＩＲなる関係式が得られる。この関係式により、第２
の測定端子から電流を流し、第１の測定端子で電圧を測
定することにより、被測定端子の端子抵抗を測定するこ
とができる。
【００１２】なお、図１において、１０，１１は半導体
アナログスイッチとしてＮチャンネル型ＭＯＳトランジ
スタで構成したが、Ｐチャンネル型ＭＯＳトランジスタ
でも、バイパーラトランジスタでも、又バイパーラトラ
ンジスタ，ダイオード等で構成されたアナログスイッチ
でもよい。また、この測定手段としては、一般に電流お
よび電圧の印加，測定をプログラムして行なう自動測定
装置が用いられるが、もちろん他の方法によつても可能
である。
【００１３】
【発明の効果】本発明は、被測定端子と別の２端子を接
続する２つのアナログスイッチを設けることにより、端
子抵抗を正確に測定することのできる半導体集積回路装
置を実現できるものである。
【図面の簡単な説明】
【図１】本発明の一実施例である半導体集積回路装置の
回路図
【図２】図１の等価回路図
【図３】従来のボンディングワイヤと半導体チップのコ
ンタクト検査をする場合の回路図
【符号の説明】
１ 第１の測定端子 ２ 第２の測定端子 ３ 被測定端子 ４，５，６ ボンディングワイヤ ７，８，９ ボンディングパッド １０，１１ Ｎチャンネルトランジスタ １２ 回路１ １３ 回路２ １４ 半導体チップ １５，１６，１７ 端子抵抗 １８，２０ トランジスタ１０を置き換えたスイッチお
よびオン抵抗 １９，２１ トランジスタ１１を置き換えたスイッチお
よびオン抵抗 ２２ 電圧計 ２３ 電流計 ２４ 外部配線抵抗 ２５ 半導体チップ ２６ Ｎ型半導体基板 ２７ Ｐ型半導体 ２８ シリコン酸化膜 ２９ 中間絶縁膜 ３０ 金属配線 ３１ 表面保護膜 ３２ ボンディングパット ３３ ボンディングワイヤ ３４ インナーリード ３５ 電源

Claims (1)

    (57)【特許請求の範囲】
  1. 【請求項１】半導体集積回路において、チップ上のボン
    ディングパッドと外部リードとこれらを電気的に接続す
    るボンディングワイヤとよりなる端子のうち、ワイヤボ
    ンディング接触抵抗を測定すべき被測定端子に近接し
    て、第１および第２の測定端子と第１および第２のアナ
    ログスイッチを設け、前記被測定端子と第１および第２
    の測定用端子とをそれぞれ第１および第２のアナログス
    イッチの入力電極および出力電極を介して接続してなる
    ことを特徴とする半導体集積回路装置。
JP2403096A 1990-12-18 1990-12-18 半導体集積回路装置 Expired - Fee Related JP2589876B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2403096A JP2589876B2 (ja) 1990-12-18 1990-12-18 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2403096A JP2589876B2 (ja) 1990-12-18 1990-12-18 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JPH04217341A JPH04217341A (ja) 1992-08-07
JP2589876B2 true JP2589876B2 (ja) 1997-03-12

Family

ID=18512854

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2403096A Expired - Fee Related JP2589876B2 (ja) 1990-12-18 1990-12-18 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JP2589876B2 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2818546B2 (ja) * 1994-12-28 1998-10-30 日本電気アイシーマイコンシステム株式会社 半導体集積回路
JP2002040114A (ja) 2000-07-26 2002-02-06 Mitsubishi Electric Corp 半導体装置

Also Published As

Publication number Publication date
JPH04217341A (ja) 1992-08-07

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