JPS57138156A - Manufacture of semiconductor integrated circuit device - Google Patents

Manufacture of semiconductor integrated circuit device

Info

Publication number
JPS57138156A
JPS57138156A JP56022238A JP2223881A JPS57138156A JP S57138156 A JPS57138156 A JP S57138156A JP 56022238 A JP56022238 A JP 56022238A JP 2223881 A JP2223881 A JP 2223881A JP S57138156 A JPS57138156 A JP S57138156A
Authority
JP
Japan
Prior art keywords
film
layer
grown
concaved sections
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56022238A
Other languages
Japanese (ja)
Other versions
JPS6152981B2 (en
Inventor
Tetsuya Takayashiki
Taiji Usui
Tetsutada Sakurai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56022238A priority Critical patent/JPS57138156A/en
Publication of JPS57138156A publication Critical patent/JPS57138156A/en
Publication of JPS6152981B2 publication Critical patent/JPS6152981B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the crystal distortion of the wafer as well as to improve the IC electric characteristics for the subject device by a method wherein an epitaxial layer is grown without using a polycrystalline Si film which will be the cause of the warpage of the wafer. CONSTITUTION:An SiO2 film 12 and an Si3N4 film 13 are laminated and coated on a P type Si substrate 11, and the prescribed pattern is formed using photography, and a plurality of concaved sections D, the wall surface of which is inclined at the desired depth, is formed by performing an anisotropic etching. Then, an SiO2 film 14 is grown on the wall surface and the bottom face of the concaved sections D by performing heat treatment, and the film 13 and the film 12 are successively removed leaving the film 14. Subsequently, a P<+> type layer 15 is formed by diffusion on the convexed surface of the substrate 11, with which the concaved sections D are pinched, the unnecessitated film 14 is removed, an N type layer 16 is epitaxially grown on the whole surface and an N type layer 17, to be used to reduce the collector resistance of an NPN bipoler transistor, is formed by diffusion on the surface layer of the layer 16. Then, the mask 18 for an SiO2 film is provided on the layer 17 located on the concaved sections D.
JP56022238A 1981-02-19 1981-02-19 Manufacture of semiconductor integrated circuit device Granted JPS57138156A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56022238A JPS57138156A (en) 1981-02-19 1981-02-19 Manufacture of semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56022238A JPS57138156A (en) 1981-02-19 1981-02-19 Manufacture of semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS57138156A true JPS57138156A (en) 1982-08-26
JPS6152981B2 JPS6152981B2 (en) 1986-11-15

Family

ID=12077210

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56022238A Granted JPS57138156A (en) 1981-02-19 1981-02-19 Manufacture of semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS57138156A (en)

Also Published As

Publication number Publication date
JPS6152981B2 (en) 1986-11-15

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