JPS57137954A - Processing state display system - Google Patents

Processing state display system

Info

Publication number
JPS57137954A
JPS57137954A JP56022788A JP2278881A JPS57137954A JP S57137954 A JPS57137954 A JP S57137954A JP 56022788 A JP56022788 A JP 56022788A JP 2278881 A JP2278881 A JP 2278881A JP S57137954 A JPS57137954 A JP S57137954A
Authority
JP
Japan
Prior art keywords
error
module
detecting part
code
firmware
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56022788A
Other languages
Japanese (ja)
Inventor
Shigemi Kawamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56022788A priority Critical patent/JPS57137954A/en
Publication of JPS57137954A publication Critical patent/JPS57137954A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine

Abstract

PURPOSE:To device proper measures quickly when a fault has occurred, by converting a firmware to a module, setting a module code to it, and adding a display routine to each module. CONSTITUTION:When a start command is given to a processor 1, modules m1, m2-mn of a firmware F are executed in order, and a series of processing are executed. When an error has occurred, its error is detected by an error detecting part 3, and an error code and an interruption request signal INT are supplied to a CPU from the error detecting part 3. Subsequently, contents of a program counter, an accumulator, etc. are saved in a stack 2S of a memory 2, and also an error code from the error detecting part 3 is loaded to a register 5. Contents of the register 5 or 7 can be displayed on an indicator by operating a switch 8. In this regard, the CPU executes an interruption routine, and after that, stops its operation.
JP56022788A 1981-02-18 1981-02-18 Processing state display system Pending JPS57137954A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56022788A JPS57137954A (en) 1981-02-18 1981-02-18 Processing state display system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56022788A JPS57137954A (en) 1981-02-18 1981-02-18 Processing state display system

Publications (1)

Publication Number Publication Date
JPS57137954A true JPS57137954A (en) 1982-08-25

Family

ID=12092412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56022788A Pending JPS57137954A (en) 1981-02-18 1981-02-18 Processing state display system

Country Status (1)

Country Link
JP (1) JPS57137954A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045850A (en) * 1983-08-22 1985-03-12 Fujitsu Ltd State display system
JPH02181231A (en) * 1989-01-05 1990-07-16 Nec Corp Data processor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045850A (en) * 1983-08-22 1985-03-12 Fujitsu Ltd State display system
JPH02181231A (en) * 1989-01-05 1990-07-16 Nec Corp Data processor

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