JPS5652451A - Interruption display system - Google Patents

Interruption display system

Info

Publication number
JPS5652451A
JPS5652451A JP12860679A JP12860679A JPS5652451A JP S5652451 A JPS5652451 A JP S5652451A JP 12860679 A JP12860679 A JP 12860679A JP 12860679 A JP12860679 A JP 12860679A JP S5652451 A JPS5652451 A JP S5652451A
Authority
JP
Japan
Prior art keywords
error
switch
memory
occurred
manual operation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12860679A
Other languages
Japanese (ja)
Inventor
Kazutoshi Michioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12860679A priority Critical patent/JPS5652451A/en
Publication of JPS5652451A publication Critical patent/JPS5652451A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to easily discriminate an error, by informing to an operator by the next manual operation and displaying the address where an error has occured and the error, in case a memory reference error has occurred at the time of memory access by the manual operation.
CONSTITUTION: It is assumed that a memory parity has occurred when a data of the main memory 5 is being read from the debug console 2. At first, when a switch A of the indicator switch 3 is set and an interruption signal is given to CPU1, CPU1 accesses the main memory 5 after reading A from the switch 3, and thrns on the address lamp A in the switch 3. And at the time of the next manual operation, a REJECT signal 9 is output to the switch 3 from the debug console 2, the REJECT lamp is turned on, and the memory address where an error interruption has occurred, and the data are informed to an operator.
COPYRIGHT: (C)1981,JPO&Japio
JP12860679A 1979-10-05 1979-10-05 Interruption display system Pending JPS5652451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12860679A JPS5652451A (en) 1979-10-05 1979-10-05 Interruption display system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12860679A JPS5652451A (en) 1979-10-05 1979-10-05 Interruption display system

Publications (1)

Publication Number Publication Date
JPS5652451A true JPS5652451A (en) 1981-05-11

Family

ID=14988927

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12860679A Pending JPS5652451A (en) 1979-10-05 1979-10-05 Interruption display system

Country Status (1)

Country Link
JP (1) JPS5652451A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59107144U (en) * 1983-01-07 1984-07-19 沖電気工業株式会社 semiconductor chip container
JPS6294650U (en) * 1985-12-03 1987-06-17

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5312079A (en) * 1976-07-20 1978-02-03 Fujitsu Ltd Method of producing multilayer printed board
JPS5330776A (en) * 1976-09-01 1978-03-23 Fujitsu Ltd Method of forming pattern on embedded land copper stacking board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5312079A (en) * 1976-07-20 1978-02-03 Fujitsu Ltd Method of producing multilayer printed board
JPS5330776A (en) * 1976-09-01 1978-03-23 Fujitsu Ltd Method of forming pattern on embedded land copper stacking board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59107144U (en) * 1983-01-07 1984-07-19 沖電気工業株式会社 semiconductor chip container
JPS6294650U (en) * 1985-12-03 1987-06-17

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