JPS57136236A - Driving semiconductor integrated circuit - Google Patents

Driving semiconductor integrated circuit

Info

Publication number
JPS57136236A
JPS57136236A JP56021076A JP2107681A JPS57136236A JP S57136236 A JPS57136236 A JP S57136236A JP 56021076 A JP56021076 A JP 56021076A JP 2107681 A JP2107681 A JP 2107681A JP S57136236 A JPS57136236 A JP S57136236A
Authority
JP
Japan
Prior art keywords
signal
plus
chip
circuits
driving circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56021076A
Other languages
Japanese (ja)
Inventor
Makoto Yamauchi
Susumu Yoshino
Hidehiko Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56021076A priority Critical patent/JPS57136236A/en
Publication of JPS57136236A publication Critical patent/JPS57136236A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/1502—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs programmable

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To decrease the timing skew between multiphase clocks, by integrating a driving circuit group containing plural sets of driving circuits connected in parallel plus an adjustable timing generating means into a chip. CONSTITUTION:Plural driving circuit groups containing AND circuits 1i, 2i and 4i(i=0-n) plus a selecting circuit 3i put into a set are connected in parallel. A chip selection signal 10i, an address signal 201 plus a read/write controlling signal 202 are applied to the driving circuit group. when an OR signal 500 of each signal 10i is set at logic 1, an FF1 is set to deliver a timing signal 401. An AND is secured between the signals 10i and 401 through the circuit 1i, and a chip clock signal 31i is delivered. Then FF2-4 are set successively with the signal delayed by a delaying circuit 7 capable of an internal adjustment. An AND is secured by the circuits 3i, 2i and 4i respectively among the output signals of the FFs 2-4 plus signals 10i, 201 and 202. Then a chip address signal 33i, a chip clock signal 32i and a read/write controlling signal 34i are delivered successively to drive a memory device.
JP56021076A 1981-02-16 1981-02-16 Driving semiconductor integrated circuit Pending JPS57136236A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56021076A JPS57136236A (en) 1981-02-16 1981-02-16 Driving semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56021076A JPS57136236A (en) 1981-02-16 1981-02-16 Driving semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS57136236A true JPS57136236A (en) 1982-08-23

Family

ID=12044792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56021076A Pending JPS57136236A (en) 1981-02-16 1981-02-16 Driving semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS57136236A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58222486A (en) * 1982-06-18 1983-12-24 Hitachi Ltd Memory integrated circuit provided with latch
JPS63228495A (en) * 1987-03-18 1988-09-22 Hitachi Ltd Mos memory

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53113435A (en) * 1977-03-14 1978-10-03 Nec Corp Memory unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53113435A (en) * 1977-03-14 1978-10-03 Nec Corp Memory unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58222486A (en) * 1982-06-18 1983-12-24 Hitachi Ltd Memory integrated circuit provided with latch
JPH0410156B2 (en) * 1982-06-18 1992-02-24
JPS63228495A (en) * 1987-03-18 1988-09-22 Hitachi Ltd Mos memory

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