JPS6419582A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce power consumption, to prevent another circuit from being affected adversely, and to perform fast reading, by providing a means to detect the input of an address signal corresponding to a nonuse address, and a control means which changes an internal operating state based on a detected result. CONSTITUTION:External control signals A0-A10 are supplied to a buffer AIBUF, and a detecting signal AV replying to the nonuse address in relation to the column of a memory cell MC is issued at a detection circuit ADRS, and an internal state is changed actually to a designated chip non-selecting state. Therefore, when all of the address signals are decoded and no corresponding memory cell exists, the power consumption can be saved. Also, a timing generating means TG issues single pulses phicd and phieg by being instructed to read information when it obtains the change of the address signal and the selection state detecting signal AV. Data can be read out at high speed by setting the level of a data line less than a balancing value for a prescribed period before starting the readout of FETs Q13 and Q14 provided at complementary data lines DL and the inverse of DL, or common data lines CDL and the inverse of CDL by the phicd and the phieg.