JPS57132452A - Terminal device for shift register type signal transmission system - Google Patents
Terminal device for shift register type signal transmission systemInfo
- Publication number
- JPS57132452A JPS57132452A JP1788381A JP1788381A JPS57132452A JP S57132452 A JPS57132452 A JP S57132452A JP 1788381 A JP1788381 A JP 1788381A JP 1788381 A JP1788381 A JP 1788381A JP S57132452 A JPS57132452 A JP S57132452A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- transmission
- master station
- terminal device
- devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Selective Calling Equipment (AREA)
- Programmable Controllers (AREA)
- Time-Division Multiplex Systems (AREA)
- Small-Scale Networks (AREA)
Abstract
PURPOSE:To optimize signal transmission between the input and output device and a central device, by using a programmable logical controller through the elimination need for a circuit establishing a higher transmission side control procedure and an address discrimination circuit. CONSTITUTION:A signal transmission system consists of a master station 1, data transmission terminal device 2, and data reception terminal device 3, both devices 2 and 3 are connected in series with a transmission line 2b, and the master station 1 is connected at both ends of transmission lines 4a and 4c from both the devices 2 and 3. The devices 2 and 3, and the master station 1 are provided with a signal discriminating circuit 12, which discriminates a data signal represented in amplitude of clock pulses from a synthesis signal from signal lines 4a-4c, to obtain a clock pulse rejecting a signal component from the signal and a master reset signal. The clock pulse and the reset signal are applied to shift registers 5, 6, 9 for a delay in a prescribed time. Without signal discrimination by the address, logic of the clock pulse is used to optimize signal transmission between the master station 1 and an input and output device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1788381A JPS57132452A (en) | 1981-02-09 | 1981-02-09 | Terminal device for shift register type signal transmission system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1788381A JPS57132452A (en) | 1981-02-09 | 1981-02-09 | Terminal device for shift register type signal transmission system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57132452A true JPS57132452A (en) | 1982-08-16 |
Family
ID=11956094
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1788381A Pending JPS57132452A (en) | 1981-02-09 | 1981-02-09 | Terminal device for shift register type signal transmission system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57132452A (en) |
-
1981
- 1981-02-09 JP JP1788381A patent/JPS57132452A/en active Pending
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