JPS57130300A - Testing circuit for read-only memory - Google Patents

Testing circuit for read-only memory

Info

Publication number
JPS57130300A
JPS57130300A JP56016122A JP1612281A JPS57130300A JP S57130300 A JPS57130300 A JP S57130300A JP 56016122 A JP56016122 A JP 56016122A JP 1612281 A JP1612281 A JP 1612281A JP S57130300 A JPS57130300 A JP S57130300A
Authority
JP
Japan
Prior art keywords
circuit
signal
outputs
address
rom20
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56016122A
Other languages
Japanese (ja)
Inventor
Yutaka Niihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56016122A priority Critical patent/JPS57130300A/en
Publication of JPS57130300A publication Critical patent/JPS57130300A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To reduce the cost of a testing circuit and the size of an external device by eliminating the need for an interface by incorporating an address driving circuit in an ROM. CONSTITUTION:The outputs of the 1st signal device 11 which outputs a signal for placing an ROM20 in a test state and the 2nd signal device 12 which outputs a signal for starting the test of the ROM20 are inputted to an AND circuit 14. The output of this AND circuit 14 and that of the 3rd signal device which outputs a clock signal are inputted to an AND circuit 15. Then, the output of the AND circuit 15 is inputted to an address counter 16. The output of the AND circuit 14 is supplied to the reset terminal R of the address counter 16 through an inverter 17. An address signal is sent from an address decoder 19 to the ROM20.
JP56016122A 1981-02-05 1981-02-05 Testing circuit for read-only memory Pending JPS57130300A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56016122A JPS57130300A (en) 1981-02-05 1981-02-05 Testing circuit for read-only memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56016122A JPS57130300A (en) 1981-02-05 1981-02-05 Testing circuit for read-only memory

Publications (1)

Publication Number Publication Date
JPS57130300A true JPS57130300A (en) 1982-08-12

Family

ID=11907701

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56016122A Pending JPS57130300A (en) 1981-02-05 1981-02-05 Testing circuit for read-only memory

Country Status (1)

Country Link
JP (1) JPS57130300A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002050199A (en) * 2000-07-13 2002-02-15 Samsung Electronics Co Ltd Non-volatile semiconductor memory having testing function

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002050199A (en) * 2000-07-13 2002-02-15 Samsung Electronics Co Ltd Non-volatile semiconductor memory having testing function

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