JPS5712537A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5712537A
JPS5712537A JP8661480A JP8661480A JPS5712537A JP S5712537 A JPS5712537 A JP S5712537A JP 8661480 A JP8661480 A JP 8661480A JP 8661480 A JP8661480 A JP 8661480A JP S5712537 A JPS5712537 A JP S5712537A
Authority
JP
Japan
Prior art keywords
thickness direction
elevated
leads
inner leads
pellets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8661480A
Other languages
Japanese (ja)
Inventor
Hiroshi Takao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8661480A priority Critical patent/JPS5712537A/en
Publication of JPS5712537A publication Critical patent/JPS5712537A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/117—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To decrease mounting space by a method wherein the pellets of a semiconductor element are juxtaposed in the thickness direction at an elevated condition, and packaged integrally, and an external lead is drawn out from one package surface in the elevated direction. CONSTITUTION:Pellets 13 are bonded to the central concave section 12 of square ceramic bases 11, erected in the elevated direction, stacked in the thickness direction and unified. Inner leads 15 reaching the external leads 14 are metallized to the base 11, difference in stages is formed in the thickness direction and short circuits among the inner leads are prevented. The external leads 14 are all concentrated and arranged to one sides of the bases 11 and soldered to the inner leads 15, and the tips are drawn out in parallel in one direction. The assembled structures are stacked in the thickness direction and glued with glass 17 with the low melting point, and a ceramic cap 18 is bonded. According to this constitution, an occupying area in a plane can be decreased largely, and a mounting structure can be miniaturized.
JP8661480A 1980-06-27 1980-06-27 Semiconductor device Pending JPS5712537A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8661480A JPS5712537A (en) 1980-06-27 1980-06-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8661480A JPS5712537A (en) 1980-06-27 1980-06-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5712537A true JPS5712537A (en) 1982-01-22

Family

ID=13891888

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8661480A Pending JPS5712537A (en) 1980-06-27 1980-06-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5712537A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58132829A (en) * 1982-01-30 1983-08-08 Canon Inc Character processing device
EP0340241A1 (en) * 1987-01-05 1989-11-08 Irvine Sensors Corp High density electronic package comprising stacked sub-modules.
US5452182A (en) * 1990-04-05 1995-09-19 Martin Marietta Corporation Flexible high density interconnect structure and flexibly interconnected system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58132829A (en) * 1982-01-30 1983-08-08 Canon Inc Character processing device
EP0340241A1 (en) * 1987-01-05 1989-11-08 Irvine Sensors Corp High density electronic package comprising stacked sub-modules.
US5452182A (en) * 1990-04-05 1995-09-19 Martin Marietta Corporation Flexible high density interconnect structure and flexibly interconnected system

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