JPS59143348A - Electronic component part - Google Patents

Electronic component part

Info

Publication number
JPS59143348A
JPS59143348A JP1733783A JP1733783A JPS59143348A JP S59143348 A JPS59143348 A JP S59143348A JP 1733783 A JP1733783 A JP 1733783A JP 1733783 A JP1733783 A JP 1733783A JP S59143348 A JPS59143348 A JP S59143348A
Authority
JP
Japan
Prior art keywords
electrodes
chip
electrode
resin
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1733783A
Other languages
Japanese (ja)
Inventor
Shigeru Otake
茂 大竹
Toshinao Saito
斎藤 敏直
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1733783A priority Critical patent/JPS59143348A/en
Publication of JPS59143348A publication Critical patent/JPS59143348A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49562Geometry of the lead-frame for devices being provided for in H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Details Of Resistors (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To miniaturize mounting dimensions and facilitate the automation of mounting by a method wherein a pair of electrodes are mounted on sides opposed to each other alternately, while projecting end parts, respectively, and then resin-molded, thereafter these end parts are bent and made to run along the molded side surfaces, when said electrodes are mounted on a semiconductor chip provided with electrodes on both surfaces back and front. CONSTITUTION:When a pair of electrodes 9 and 10 composed of Cu, etc. mounted on both surfaces front and back of the diode chip 11 wherein a semi-spherical bump electrode is adhered on the surface, and an opposition electrode on the back surface, recesses 13 for preventing slip-out are provided at side edge parts of these electrodes 9 and 10, and the end parts of these electrodes 9 and 10 are alternately extended out of the chip 11. Thereafter, these are molded with resin 8, the external extending parts of the electrodes 9 and 10 are bent, thus being made to run along the side surface of the resin 8. Accordingly, the electronic component parts are miniaturized and then made appropriate for automatic assembly.

Description

【発明の詳細な説明】 本発明は電子部品、4Iダイオード、抵抗、コンデンサ
等の2つの電極會有するzJs型の電子部品に関する〇 従来、ダイオードとして、第1図(a)〜(c)に示す
構造が知られている。同図←)は1対のヌラグリード1
の太径端面間にチップ(図示せず)を挾持するとともに
ガラス管2でチップ等を封止したダブルヒートシンクダ
イオード(DHD)である。同図(1,、)はレジンパ
ッケージ3の一側面から2本のリード4を突出させたレ
ジンパッケージ型ダイオードである。このダイオードは
一方のリードの内端にチップ(図示せず)を固定しであ
る。また、他方のリードの内端とチップの電極とはワイ
ヤ(図示せず)で接続されている。そして、両リードの
内端およびチップ、ワイヤがレジンパッケージ3で封止
されている。さらに、同図(C)は1苅の段付電極5の
小径端面間にチップ(図示せず)′に挟持きせるととも
に、小径部、チップ、小径部に亘る部分をガラス管6で
封止した構造となっている。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to electronic components, zJs type electronic components having two electrodes, such as 4I diodes, resistors, and capacitors. structure is known. The figure ←) shows a pair of Nura Greed 1.
This is a double heat sink diode (DHD) in which a chip (not shown) is sandwiched between the large-diameter end faces of the double heat sink diode (DHD), and the chip and the like are sealed with a glass tube 2. The figure (1, ,) shows a resin package type diode in which two leads 4 are made to protrude from one side of a resin package 3. This diode has a chip (not shown) fixed to the inner end of one lead. Further, the inner end of the other lead and the electrode of the chip are connected by a wire (not shown). The inner ends of both leads, the chip, and the wires are sealed with a resin package 3. Furthermore, in the same figure (C), a tip (not shown)' is sandwiched between the small diameter end faces of one stepped electrode 5, and the portion covering the small diameter part, the tip, and the small diameter part is sealed with a glass tube 6. It has a structure.

しかし、これらのダイオードは以下のような難点がある
However, these diodes have the following drawbacks.

(1)、DHDおよびレジンパッケージ型ダイオードは
その実装におっては、リードを配線基板の取付孔に挿入
しなければならないが、このリードの自動挿入化は難し
い。捷た、こねらのダイオードは実装時の高さが2〜3
mgと高い。
(1) When mounting DHDs and resin packaged diodes, the leads must be inserted into the mounting holes of the wiring board, but it is difficult to automatically insert the leads. The height of the assembled diode is 2 to 3 when mounted.
mg and high.

(2)、第1図(c)に示す段付1!極構造は配線基板
上に載置(、その状態で段付電極の大径部に半田を付け
て実装するいわゆる面取付構造となっていて、実装の自
動化がし易いとともに、実装高さもたとえば1.5 w
s程度と小さくできる特長があるが、長さがたとえば3
.5閣と末だ長く、全体として大きい。
(2), step 1 shown in FIG. 1(c)! The electrode structure is a so-called surface mount structure in which the large diameter part of the stepped electrode is mounted on the wiring board by soldering it in that state, making it easy to automate the mounting, and the mounting height can be reduced to, for example, 1. .5w
It has the advantage that it can be made as small as 3.
.. It is long with five temples, and is large as a whole.

したがって、本発明の目的は実装の自動化が容易でかつ
実装寸法が小さくなる小型の電子部品を提供することに
ある。
Therefore, an object of the present invention is to provide a small electronic component whose mounting can be easily automated and whose mounting dimensions are small.

第2図は本発明の一実施例によるダイオードの断面図、
第3図(a)〜(C)は同じくダイオードの組立方法を
示す酬親図訃よび断面図、第4図は同じく実装状態を示
す断面図である。
FIG. 2 is a cross-sectional view of a diode according to an embodiment of the present invention;
3(a) to 3(C) are schematic diagrams and cross-sectional views showing the method of assembling the diode, and FIG. 4 is a cross-sectional view showing the mounting state.

実施例のダイオード7は第2図に示すように、直方体の
レジンからなるパッケージ8と、このパリケージ8の一
端下部に内端を臨オゼ、外端全パッケージ8の一端面に
沿うように突出部で上方に折り曲げり電極板9と、前記
パッケージ8の他端上部に内端を臨1ゼ、外端全パ・ン
ケージ8の他端面に沿うように突出部で下方に折り曲げ
た電極板10と、前記1対の電極板9,10の相互に軍
な9合うように対峙された電極板部分間に挾持固定され
たチップ11と、からなっている。チップ11はダイオ
ード素子となることから、チップ11の表裏面(上下面
)に111tj12’に有している。そして、チップ1
1は両電極12を介してそれぞれ電極板9.10の互に
逆となる端部に電気的機械的に接続されている。また、
両電極板9,10はレジンパッケージ8から抜けないよ
うな後述する引掛部が設けられている。
As shown in FIG. 2, the diode 7 of the embodiment includes a rectangular parallelepiped resin package 8, an inner end bent at the lower end of the paris cage 8, and a protruding portion extending along one end surface of the entire outer end of the package 8. An electrode plate 9 is bent upward at the upper end of the package 8, and an electrode plate 10 is bent downward at the protruding part so that the inner end is aligned with the upper part of the other end of the package 8, and the entire outer end is along the other end surface of the package 8. , and a chip 11 which is clamped and fixed between the electrode plate portions of the pair of electrode plates 9 and 10 which are opposed to each other so as to be aligned with each other. Since the chip 11 serves as a diode element, it has 111tj12' on the front and back surfaces (upper and lower surfaces) of the chip 11. And chip 1
1 are electrically and mechanically connected via both electrodes 12 to mutually opposite ends of the electrode plates 9, 10, respectively. Also,
Both electrode plates 9 and 10 are provided with hook portions, which will be described later, to prevent them from coming off the resin package 8.

つぎに、第3図(a)〜(Q)を弁開しながら実施例の
ダイオードを組み立てる方法について説明する。
Next, a method of assembling the diode of the embodiment while opening the valves in FIGS. 3(a) to 3(Q) will be explained.

先づ、1対の電極板9,10およびチップ(ダイオード
チップ)11″ft用意する。チップ11は縦横の寸法
がたとえば04μm、厚さく高さ)が02μmとなって
いて、表面(上面)の中央には50μm程度の高さの銀
からなる半球状のバンプを極(電極)12が設けられて
いる。また、チップ11の裏面(下面)には数千Aの厚
さの釧からなる11r極(図示せず)が設けられている
。1対の電極板9.10は幅はチップ110幅(横)と
同和度(大きくとも小さくともよい。)、長さはチップ
11の縦の長さよシも長くなっている。また、電極板9
,10は銅、コバール等一般にリード電極として用いら
れる材質で形成されるが、その厚さは取り扱い時に切れ
たりあるいは電極として不都合を来たさないこと全限度
々してできるだけ薄くする。また、1対の電極板9.1
0は互に逆とがる端部會チップ11に対面させる。!!
、fc、このチップ対面部分は後述するようにレジンノ
くクケージによって被われるが、その際、これらt極板
9゜10がレジンパッケージ8から抜けないように11
拐部13が設けられている。引掛部13は電極板9,1
00両側を部分的に窪ませることによって形成されてい
るが、他の構造としては、電極板9.10の両側に設け
る突起あるいは電極板9゜10に穿った孔等によっても
形成できる。
First, a pair of electrode plates 9 and 10 and a chip (diode chip) of 11" ft are prepared. The chip 11 has length and width dimensions of, for example, 04 μm, thickness (height) of 0.02 μm, and a surface (upper surface) of the chip 11. A pole (electrode) 12 is provided in the center, which is a hemispherical bump made of silver with a height of about 50 μm.In addition, on the back surface (lower surface) of the chip 11, there is provided an electrode 12 made of a hemispherical bump made of silver with a thickness of several thousand amps. A pair of electrode plates 9 and 10 has a width that is the same as the width (horizontal) of the chip 110 (which may be larger or smaller), and a length that is equal to the vertical length of the chip 11. The parting is also longer.Also, the electrode plate 9
, 10 are made of a material commonly used for lead electrodes, such as copper or Kovar, and their thickness is made to be as thin as possible so that they do not break during handling or cause any inconvenience as electrodes. In addition, a pair of electrode plates 9.1
0 face the mutually oppositely pointed ends 11. ! !
, fc, this chip facing part is covered with a resin cage as described later, but at that time, 11
A cover section 13 is provided. The hook part 13 is connected to the electrode plates 9, 1
Although it is formed by partially recessing both sides of the electrode plate 9, 10, other structures may be formed by protrusions provided on both sides of the electrode plate 9, 10, or holes bored in the electrode plate 9, 10.

そこで、第3図(a)に示すように、1対の電極板9.
10の互に逆と力る端部間にチップ11會挾み、加圧加
熱によってw接部の舒會利用してチップ11と電極板9
.10を電気的機械的に接続させる。
Therefore, as shown in FIG. 3(a), a pair of electrode plates 9.
The chip 11 is sandwiched between the mutually opposing ends of the electrode plate 9, and the chip 11 and the electrode plate 9 are connected by applying heat and pressure to connect the w-contact part.
.. 10 are electrically and mechanically connected.

つぎに、同図Cb)に示すように、チップ11およびチ
ップ11を支持する電極板部分をレジンモールドしてレ
ジンパッケージ8で被う。
Next, as shown in FIG. Cb), the chip 11 and the electrode plate portion supporting the chip 11 are resin molded and covered with a resin package 8.

つぎに、同図(C)に示すように、レジンパリケージ8
から突出する電極板部分を突出部で折り曲げ、レジンパ
・ンケージ8の端面に沿うようにする。す女わち、下方
の電極板9は上方に折シ曲げ、上方の電極板10は下方
に折シ曲げる。なお、折シ曲げの先端はパッケージ8の
上下面から突出し力いようにあらかじめ電極板9,10
の長さを設定しておく。
Next, as shown in the same figure (C), the resin pari cage 8
The electrode plate portion protruding from the electrode plate is bent at the protruding portion so as to fit along the end surface of the resin package 8. That is, the lower electrode plate 9 is bent upward, and the upper electrode plate 10 is bent downward. Note that the electrode plates 9 and 10 are bent in advance so that the bent ends protrude from the upper and lower surfaces of the package 8.
Set the length.

このようなダイオード7はその実装にあっては、第4図
に示すように配線基板14上に載置し、この状態で半田
15會介して接続する。バクケージ80両端に露出する
電極板9,10は半田15を介して配線基板14の配線
層16に電気的機械的に接続される。
When mounting such a diode 7, it is placed on a wiring board 14 as shown in FIG. 4, and connected in this state through solder 15. Electrode plates 9 and 10 exposed at both ends of back cage 80 are electrically and mechanically connected to wiring layer 16 of wiring board 14 via solder 15.

このようなダイオード7のパッケージ8の縦横の大きさ
はチップ11の縦横の寸法よシもわずかに大きいだけで
よく、また、高さもチップ110埋さおよび電極板2枚
の厚さとレジンの被う厚さだけでよい。さらに、薄い電
極板9.10はパッケージ8の端面に延在する構造とな
っている。この結果、実施例のダイオードの全体の寸法
は従来品よりも小型化され、たとえば、縦横が1.5 
m 。
The vertical and horizontal dimensions of the package 8 for the diode 7 need only be slightly larger than the vertical and horizontal dimensions of the chip 11, and the height also depends on the depth of the chip 110, the thickness of the two electrode plates, and the resin covering. All you need is the thickness. Furthermore, the thin electrode plates 9 and 10 are structured to extend over the end face of the package 8. As a result, the overall dimensions of the diode of the example are smaller than those of conventional products, for example, the length and width are 1.5
m.

高さが1園と極めて小型化される。したがって、本実施
例ダイオードは実装寸法、特に高さ寸法が小さくできる
The height is extremely small, just one garden. Therefore, the mounting dimensions, especially the height dimensions, of the diode of this embodiment can be reduced.

また、本実施列ダイオードは面取付構造となっているこ
とから、実装時の供給自動化本容易となり、実装の自動
化も容易となる。
Furthermore, since the present array diode has a surface mounting structure, it is easy to automate the supply during mounting, and the automation of mounting is also facilitated.

なお、本発明は前記実施列に限定されない。たとえば、
第5図に示すように、T部の電極板9にあっては、チッ
プ11を取り付けた面(チップ取付面)の裏面はレジン
パッケージ8で被わないようにしてもよい。この場合に
はダイオード7の高さ寸法がさらに低くなる特長が生じ
るとともに、一方の電極はレジンパッケージ8の下面に
位置するため、配線基板14の設計の自由度も増大する
Note that the present invention is not limited to the above embodiments. for example,
As shown in FIG. 5, in the electrode plate 9 of the T portion, the back surface of the surface on which the chip 11 is mounted (chip mounting surface) may not be covered with the resin package 8. In this case, the height of the diode 7 is further reduced, and since one electrode is located on the lower surface of the resin package 8, the degree of freedom in designing the wiring board 14 is increased.

また、第6図は前記第5図に示す実施例の改良型であっ
て、レジンパッケージ8の下面に位置する電極板9はレ
ジンパッケージ8の端面に突出させない構造としている
。この構造では第5図の実施例に生じる効果に加えて、
ダイオード7の縦方向の寸法が電極板の厚さ分だけ短か
くなることから、さらに小型化が図れることになる。
FIG. 6 is an improved version of the embodiment shown in FIG. 5, in which the electrode plate 9 located on the lower surface of the resin package 8 does not protrude from the end surface of the resin package 8. With this structure, in addition to the effects produced in the embodiment of FIG.
Since the vertical dimension of the diode 7 is reduced by the thickness of the electrode plate, further miniaturization can be achieved.

本発明はダイオード以外の抵抗、コンデンサ。The present invention relates to resistors and capacitors other than diodes.

あるいは他の半導体装置にも適用することができる。Alternatively, it can be applied to other semiconductor devices.

以上のように、本発明によれば、実装の自動化が容易で
かつ実装寸法が小さくなる小型の電子部品會提供するこ
とができる。
As described above, according to the present invention, it is possible to provide a compact electronic component assembly whose mounting can be easily automated and whose mounting dimensions are small.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(c)は従来のダイオードを示す正面図
、第2図は本発明の一実施例によるダイオードの断面図
、 第3図(、)〜(c)は同じくダイオードの組立方法を
示す側視図および断面図、 第4図は同じく実装状態を示す断面図、第5図は他の実
施例によるダイオードの断面図、第6図は他の実施例に
よるダイオードの断面図である。 7・・・ダイオード、8・・・パッケージ、9,1o・
・・電極板、11・・チップ、12・・・電極、14・
・・配線基板、15・・・半田、16・・・配線層。 (9)。 第  4 図 −240− 第  6 図
Figures 1 (a) to (c) are front views showing a conventional diode, Figure 2 is a sectional view of a diode according to an embodiment of the present invention, and Figures 3 (,) to (c) are the same diode assembly. A side view and a sectional view showing the method, FIG. 4 is a sectional view showing the mounting state, FIG. 5 is a sectional view of a diode according to another embodiment, and FIG. 6 is a sectional view of a diode according to another embodiment. be. 7...Diode, 8...Package, 9,1o・
...electrode plate, 11...chip, 12...electrode, 14.
...Wiring board, 15...Solder, 16...Wiring layer. (9). Figure 4-240- Figure 6

Claims (1)

【特許請求の範囲】 1、互いに逆となる端部が相互に重なるように配設され
fc1対の電極板と、これら電極板間に挾持これかつ電
極を介して電気的機械的に接続された表裏面に電極を有
するチップと、このチップおよびチップを支える電極板
部分を被うレジンからなるパッケージと、からなシ、前
記パッケージから突出するチップを支えない電極板部分
は突出部分で折゛れ曲がってバグケージの端面に沿って
延在していることを特徴とする電子部品。 2、前記一方の電極板のチップ取付面の裏面はパッケー
ジから露出していることを特徴とする特許請求の範囲第
1項記載の電子部品。
[Scope of Claims] 1. A pair of fc electrode plates disposed such that their opposite ends overlap each other, and a pair of fc electrode plates sandwiched between these electrode plates and electrically and mechanically connected via the electrodes. A package consisting of a chip that has electrodes on the front and back sides, a resin package that covers the chip and the electrode plate part that supports the chip, and a shell that protrudes from the package and the part of the electrode plate that does not support the chip is folded at the protruding part. An electronic component characterized in that it is curved and extends along the end face of the bug cage. 2. The electronic component according to claim 1, wherein the back surface of the chip mounting surface of the one electrode plate is exposed from the package.
JP1733783A 1983-02-07 1983-02-07 Electronic component part Pending JPS59143348A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1733783A JPS59143348A (en) 1983-02-07 1983-02-07 Electronic component part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1733783A JPS59143348A (en) 1983-02-07 1983-02-07 Electronic component part

Publications (1)

Publication Number Publication Date
JPS59143348A true JPS59143348A (en) 1984-08-16

Family

ID=11941231

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1733783A Pending JPS59143348A (en) 1983-02-07 1983-02-07 Electronic component part

Country Status (1)

Country Link
JP (1) JPS59143348A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5712197A (en) * 1995-05-12 1998-01-27 U.S. Philips Corporation Method of manufacturing a semiconductor device suitable for surface mounting
JP2005051130A (en) * 2003-07-31 2005-02-24 Nec Electronics Corp Leadless package semiconductor device and method for manufacturing the same
JP2006060255A (en) * 2005-11-07 2006-03-02 Nec Electronics Corp Leadless package semiconductor device
CN104319268A (en) * 2013-11-05 2015-01-28 立昌先进科技股份有限公司 Chip-type diode package device and method for fabricating the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5712197A (en) * 1995-05-12 1998-01-27 U.S. Philips Corporation Method of manufacturing a semiconductor device suitable for surface mounting
JP2005051130A (en) * 2003-07-31 2005-02-24 Nec Electronics Corp Leadless package semiconductor device and method for manufacturing the same
US7224045B2 (en) 2003-07-31 2007-05-29 Nec Electronics Corporation Leadless type semiconductor package, and production process for manufacturing such leadless type semiconductor package
JP2006060255A (en) * 2005-11-07 2006-03-02 Nec Electronics Corp Leadless package semiconductor device
CN104319268A (en) * 2013-11-05 2015-01-28 立昌先进科技股份有限公司 Chip-type diode package device and method for fabricating the same

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