JPS57125376A - Circuit for functioning/testing of ic for watch - Google Patents

Circuit for functioning/testing of ic for watch

Info

Publication number
JPS57125376A
JPS57125376A JP56011078A JP1107881A JPS57125376A JP S57125376 A JPS57125376 A JP S57125376A JP 56011078 A JP56011078 A JP 56011078A JP 1107881 A JP1107881 A JP 1107881A JP S57125376 A JPS57125376 A JP S57125376A
Authority
JP
Japan
Prior art keywords
circuit
resetting
outputs
terminal
watch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56011078A
Other languages
Japanese (ja)
Inventor
Taira Yagi
Hiroshi Oda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56011078A priority Critical patent/JPS57125376A/en
Publication of JPS57125376A publication Critical patent/JPS57125376A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G04HOROLOGY
    • G04GELECTRONIC TIME-PIECES
    • G04G5/00Setting, i.e. correcting or changing, the time-indication

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Electric Clocks (AREA)
  • Electromechanical Clocks (AREA)

Abstract

PURPOSE:To enable a terminal to set 3 conditions of a watch by a simple mechanism, by controlling opening and closing of a gate and resetting of a counter in accordance with 3-value signal including floating level. CONSTITUTION:When a reset/test terminal 100 is opened to set condition of floating, outputs TQ1 of an inverter 40 and a D type FF 41 and outputs Q2 of an exlusive OR gate 42 and a D type FF 43, etc., to which this outputs Q1 and Q1 passing through inverters 45 and 46 are added, are logically treated by a logical circuit 44, so that outputs ACC and RESET all become logically zero (0). Similarly, by variation of logical values of signals ACC and RESET put out from the circuit 44 in accordance with logic 1 or 0 of a signal added to the terminal 100, opening and resetting of clocked inverters 35 and 34, which form a gate, and resetting of a static frequency dividing circuit 36 are controlled. By doing so, 3 conditions of a step motor including the mormal operation, the resetting and the testing acceleration by frequency dividing output of high frequency are all done by a terminal, and therefore, a circuit for the both functioning and testing of IC for watch is obtained by a simple mechanism.
JP56011078A 1981-01-28 1981-01-28 Circuit for functioning/testing of ic for watch Pending JPS57125376A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56011078A JPS57125376A (en) 1981-01-28 1981-01-28 Circuit for functioning/testing of ic for watch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56011078A JPS57125376A (en) 1981-01-28 1981-01-28 Circuit for functioning/testing of ic for watch

Publications (1)

Publication Number Publication Date
JPS57125376A true JPS57125376A (en) 1982-08-04

Family

ID=11767940

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56011078A Pending JPS57125376A (en) 1981-01-28 1981-01-28 Circuit for functioning/testing of ic for watch

Country Status (1)

Country Link
JP (1) JPS57125376A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62116271A (en) * 1985-11-15 1987-05-27 Fujitsu Ltd Test circuit
JP2010071729A (en) * 2008-09-17 2010-04-02 Mitsumi Electric Co Ltd Semiconductor integrated circuit for driving motor and method for testing
JP2011013120A (en) * 2009-07-02 2011-01-20 Seiko Instruments Inc Integrated circuit for electronic clock, and electronic clock

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62116271A (en) * 1985-11-15 1987-05-27 Fujitsu Ltd Test circuit
JPH0644031B2 (en) * 1985-11-15 1994-06-08 富士通株式会社 Test circuit
JP2010071729A (en) * 2008-09-17 2010-04-02 Mitsumi Electric Co Ltd Semiconductor integrated circuit for driving motor and method for testing
JP2011013120A (en) * 2009-07-02 2011-01-20 Seiko Instruments Inc Integrated circuit for electronic clock, and electronic clock

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