JPS54162517A - Pulse generating circuit for servo circuit of home vtr - Google Patents

Abstract

PURPOSE: To readily generate two pulse widths and achieve the reduction of the number of terminals of ICs by opening and closing only one of NAND gates by a switching singnal.

CONSTITUTION: Where no trigger signal 26 is inputted, the output 29 is level "L" and NAND gates 35, 36 are settled in the state of close and open, respectively, but when the signal 26 is inputted, FFs 30 thru 34 are all reset and the Q outputs of the respective FFs become "L". The output 29 then becomes "H". Because of this, the gates 35, 36 invert to open and close, respectively, then the clock signal 23 inputs to the T input of the FF 30 which in turn starts frequency division. As the frequency division progresses and when all the NAND gates 37 become "H", the output 29 returns to "L" and the gate 35 closes to stop the frequency division, thus waiting for the input of the signal 26. Hence, if the dividing frequencies are determined by the FFs 30, 33, 34 by making the switching signal 28 "L" and closing the gate 38 at the recording and by the FFs 30, 33, 34 and 32 by reversing the conditions from the above at the reproducing, the arbitrary two pulse widths may be readily generated.

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