JPS57123716A - Digital filter - Google Patents

Abstract

PURPOSE:To eliminate the influence of an overflow by constituting a multiplier which performs continuous arithmetic regarding only significant data length without any excessive bit, and inserting 0 into the contents of a register in accordance with the number of parameters on detecting an overflow of the arithmetic result. CONSTITUTION:A digital filter consists of a multiplier MPL, an adder (+), a subtracter (-), delay registers DR1-DR3, a partialsum register REG, and a register ZR, and performs digital arithmetic processing on pipeline basis. The MPL is constituted by cascading an initial-stage module, a basic module, a discarding module, and a final-stage module, and performs continuous arithmetic regarding only significant data length without any excessive bit. A control circuit DCNT when detecting an overflow of the arithmetic result at the final stage of an arithmetic loop sends 0 to close gates G1-G6, thereby inserting the 0 into the DR1-DR3 only in a period which corresponds to parameters. The coefficients F of the MPL are inputted successively on time-division mode, and an input L(t) and timing are adjusted by the register ZR, thereby sending an output W(t) from a gate G3 synchronously with an output synchronizing signal SYN.