JPS57121351A - Receiving device for time series signal - Google Patents

Receiving device for time series signal

Info

Publication number
JPS57121351A
JPS57121351A JP817581A JP817581A JPS57121351A JP S57121351 A JPS57121351 A JP S57121351A JP 817581 A JP817581 A JP 817581A JP 817581 A JP817581 A JP 817581A JP S57121351 A JPS57121351 A JP S57121351A
Authority
JP
Japan
Prior art keywords
time
tau
circuits
output
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP817581A
Other languages
Japanese (ja)
Inventor
Fumiya Nagata
Moichi Hirasawa
Satoshi Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP817581A priority Critical patent/JPS57121351A/en
Publication of JPS57121351A publication Critical patent/JPS57121351A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042—Detectors therefor, e.g. correlators, state machines

Abstract

PURPOSE:To increase the number of bits to be monitored for pattern coincidence detection equivalently, by providing additionally a delay circuit in the output terminal of an OR circuit. CONSTITUTION:Delay circuits 6a-6c are provided additionally in output terminals of PR circuits 4a-4c respectively, and coincidence detection signals 5a- 5c transmitted from these OR circuits are delayed by a time corresponding to tau-number bits, and these delayed output signals and output signals of OR circuits are operated for AND by AND circuits 7a-7c to obtain pattern coincidence detection signals 8a-8c of respective time series signals. For example, the output 8a of the AND circuit 7a coincides with a specific pattern from a time t-n to a time (t) and from a time t-tau-n to a time t-tau, namely, from the time t-tau-n to the time (t), and as the result, (n+tau)-number bits coincide with the specific pattern, and thus, a shift register 2 is extended to n+tau equivalently.
JP817581A 1981-01-21 1981-01-21 Receiving device for time series signal Pending JPS57121351A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP817581A JPS57121351A (en) 1981-01-21 1981-01-21 Receiving device for time series signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP817581A JPS57121351A (en) 1981-01-21 1981-01-21 Receiving device for time series signal

Publications (1)

Publication Number Publication Date
JPS57121351A true JPS57121351A (en) 1982-07-28

Family

ID=11685978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP817581A Pending JPS57121351A (en) 1981-01-21 1981-01-21 Receiving device for time series signal

Country Status (1)

Country Link
JP (1) JPS57121351A (en)

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