JPS5769577A - Address circuit - Google Patents

Address circuit

Info

Publication number
JPS5769577A
JPS5769577A JP14472080A JP14472080A JPS5769577A JP S5769577 A JPS5769577 A JP S5769577A JP 14472080 A JP14472080 A JP 14472080A JP 14472080 A JP14472080 A JP 14472080A JP S5769577 A JPS5769577 A JP S5769577A
Authority
JP
Japan
Prior art keywords
address
signals
signal
reset
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14472080A
Other languages
Japanese (ja)
Inventor
Yoshihiro Nakaoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP14472080A priority Critical patent/JPS5769577A/en
Publication of JPS5769577A publication Critical patent/JPS5769577A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

PURPOSE:To unify address circuits to be connected to the outside to one circuit, and to remove a malfunction by a simple constitution, by counting an address clock positioned between reset signals which are superposed on a data signal, and obtaining an address signal. CONSTITUTION:Data signals D1-D4 on which a reset signal SR and a carry signal SC have been superposed from input terminals 1-4 are supplied to a memory 5, a reset discriminating circuit 6 and a latching circuit 7, respectively. A counter 8 of an address clock is reset whenever the signal SR is detected, and the data signal is synchronized with the address clock. Output signals Q1-Q3 of the counter 8 are supplied to the memory 5 as address signals A1-A3, respectively, and also to a carry discriminating circuit 10. As a result, the lowest rank digit of the address is designated by signals A0-A3, an upper digit than the lowest rank digit is designated by signals A4-A7, and the signals D1-D4 are stored in the prescribed address.
JP14472080A 1980-10-16 1980-10-16 Address circuit Pending JPS5769577A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14472080A JPS5769577A (en) 1980-10-16 1980-10-16 Address circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14472080A JPS5769577A (en) 1980-10-16 1980-10-16 Address circuit

Publications (1)

Publication Number Publication Date
JPS5769577A true JPS5769577A (en) 1982-04-28

Family

ID=15368734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14472080A Pending JPS5769577A (en) 1980-10-16 1980-10-16 Address circuit

Country Status (1)

Country Link
JP (1) JPS5769577A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61851A (en) * 1984-06-14 1986-01-06 Nec Corp Data chain system of direct memory access circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61851A (en) * 1984-06-14 1986-01-06 Nec Corp Data chain system of direct memory access circuit

Similar Documents

Publication Publication Date Title
ES8405218A1 (en) Level sensitive reset circuit for digital logic.
JPS5769577A (en) Address circuit
JPS6466730A (en) Adder
JPS535549A (en) Voltage comparison circuit
JPS5534572A (en) Counting circuit
JPS5310467A (en) Electronic timepiece with multiple alarms
JPS53118327A (en) Automatic test data generator
JPS56100520A (en) Pulse processing circuit
JPS55162144A (en) Assigning circuit for number of digits of transmitted data
JPS5798040A (en) Comparator for serial magnitude
JPS5657327A (en) Chattering eliminating circuit
JPS5613849A (en) Data transmitting device
JPS52144253A (en) Flip-flop circuit
JPS5679534A (en) Initial set system
JPS54125078A (en) Timer
JPS5399716A (en) Clamp circuit
JPS567129A (en) Device selection circuit
JPS567520A (en) Chattering rejection circuit
JPS56106451A (en) Multiplication/isolation circuit
JPS5275236A (en) Signal processing circuit
JPS53146548A (en) Resetting device for shift register
JPS55129841A (en) Check circuit for input signal number
JPS55120221A (en) Phase difference detection circuit of digital circuit
JPS57121351A (en) Receiving device for time series signal
JPS5577092A (en) Integrated circuit