JPS5577092A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS5577092A
JPS5577092A JP14900578A JP14900578A JPS5577092A JP S5577092 A JPS5577092 A JP S5577092A JP 14900578 A JP14900578 A JP 14900578A JP 14900578 A JP14900578 A JP 14900578A JP S5577092 A JPS5577092 A JP S5577092A
Authority
JP
Japan
Prior art keywords
ffs
register
value
signal
circulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14900578A
Other languages
Japanese (ja)
Inventor
Haruo Yano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14900578A priority Critical patent/JPS5577092A/en
Publication of JPS5577092A publication Critical patent/JPS5577092A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers

Landscapes

  • Shift Register Type Memory (AREA)

Abstract

PURPOSE:To make it possible to return easily the value of FF to that before the occurrence of a fault while a data process is retried, by making fixed connections among several FFs forming a registor. CONSTITUTION:For example, register, 1 is composed of five FFs 7-11; only FF7 has external input and output and FF7-FF11 are so connected that a function of circulating will be given. Similarly, registers 2-4 are formed. In normal operation, the value of input signal 31 is set to FF7 by command signal 35 from external terminal 17 and values one to four clocks before are held by FFs 8-11. Once a data processor is detected getting out of order, the polarity of signal 35 is inverted and register 1 is operated as a circulating shift register. As a result, values held by FFs 11-8 are sequentially set to FF7 and outputted. In this way, the processor can be placed in the state before the fault occurs.
JP14900578A 1978-12-04 1978-12-04 Integrated circuit Pending JPS5577092A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14900578A JPS5577092A (en) 1978-12-04 1978-12-04 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14900578A JPS5577092A (en) 1978-12-04 1978-12-04 Integrated circuit

Publications (1)

Publication Number Publication Date
JPS5577092A true JPS5577092A (en) 1980-06-10

Family

ID=15465572

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14900578A Pending JPS5577092A (en) 1978-12-04 1978-12-04 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS5577092A (en)

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