JPS57121352A - Receiving device for time series signal - Google Patents
Receiving device for time series signalInfo
- Publication number
- JPS57121352A JPS57121352A JP817681A JP817681A JPS57121352A JP S57121352 A JPS57121352 A JP S57121352A JP 817681 A JP817681 A JP 817681A JP 817681 A JP817681 A JP 817681A JP S57121352 A JPS57121352 A JP S57121352A
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuits
- bit
- coincidence detection
- error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
- H04L7/042—Detectors therefor, e.g. correlators, state machines
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Communication Control (AREA)
Abstract
PURPOSE:To correct a bit error to obtain a sure pattern coincidence detection output, by providing additionally a delay circuit, which delays the output of an OR circuit by a prescribed number of bits, in the output terminal of the OR circuit. CONSTITUTION:Delay circuits 6a-6c are provided additionally in respective output terminals of OR circuits 4a-4c, and pattern coincidence detection signals transmitted from OR circuits are delayed by n-number bits, and these delayed output signals and output signals of OR circuits 4a-4c are operated for AND by AND circuits 7a-7c to obtain pattern coincidence detection signals 8a-8c. If an one-bit error occurs on the line, the pattern coincidence detection output is zero for a time corresponding to n-number bits from the input of this bit to a shift register 2 to the output of this bit after n-bit shift, and thus, the one- bit error in receiving is detected. This error is corrected by delay circuits and OR circuits, and the coincidence detection output with the error corrected is obtained.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP817681A JPS57121352A (en) | 1981-01-21 | 1981-01-21 | Receiving device for time series signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP817681A JPS57121352A (en) | 1981-01-21 | 1981-01-21 | Receiving device for time series signal |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57121352A true JPS57121352A (en) | 1982-07-28 |
Family
ID=11686002
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP817681A Pending JPS57121352A (en) | 1981-01-21 | 1981-01-21 | Receiving device for time series signal |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57121352A (en) |
-
1981
- 1981-01-21 JP JP817681A patent/JPS57121352A/en active Pending
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