JPS57160224A - Count confirming circuit - Google Patents

Count confirming circuit

Info

Publication number
JPS57160224A
JPS57160224A JP4512181A JP4512181A JPS57160224A JP S57160224 A JPS57160224 A JP S57160224A JP 4512181 A JP4512181 A JP 4512181A JP 4512181 A JP4512181 A JP 4512181A JP S57160224 A JPS57160224 A JP S57160224A
Authority
JP
Japan
Prior art keywords
circuit
carry
inputted
signal
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4512181A
Other languages
Japanese (ja)
Inventor
Shigeru Miyajima
Akihiro Maruo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4512181A priority Critical patent/JPS57160224A/en
Publication of JPS57160224A publication Critical patent/JPS57160224A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation

Landscapes

  • Error Detection And Correction (AREA)

Abstract

PURPOSE:To confirm the prepriety of the carrying of a low-order byte counting circuit by inputting a low-order byte signal to an NAND circuit, and then inputting its output and a carry signal to an AND circuit. CONSTITUTION:For a carry from a byte counter BC1-4 to a BC1-3, an AND circuit 5 outputs a carry signal when the most significant digit bits CO4-CO6 of a BC circuit 4 go up to 1s respectively. This carry signal is inputted to one input terminal of the AND circuit 11 of carry confirming circuit 10 added separately. All bit signals of the BC1-4 to be carried are inputted to an NAND circuit 12. Bits C4-0-C4-7 should all be 1s for carrying, and all 1s are inputted to the circuit 12, which outputs a 0. This 0 signal and a carry signal 1 are inputted to an AND circuit 11, which outputs a 0, thus detecting the carry signal having no error. If one of bits of the BC1-4 is a 0, the circuit 11 outputs a 1, showing that there is an error in carrying.
JP4512181A 1981-03-27 1981-03-27 Count confirming circuit Pending JPS57160224A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4512181A JPS57160224A (en) 1981-03-27 1981-03-27 Count confirming circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4512181A JPS57160224A (en) 1981-03-27 1981-03-27 Count confirming circuit

Publications (1)

Publication Number Publication Date
JPS57160224A true JPS57160224A (en) 1982-10-02

Family

ID=12710432

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4512181A Pending JPS57160224A (en) 1981-03-27 1981-03-27 Count confirming circuit

Country Status (1)

Country Link
JP (1) JPS57160224A (en)

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