JPS56120224A - Coincidence circuit for time sharing type counter - Google Patents
Coincidence circuit for time sharing type counterInfo
- Publication number
- JPS56120224A JPS56120224A JP2428480A JP2428480A JPS56120224A JP S56120224 A JPS56120224 A JP S56120224A JP 2428480 A JP2428480 A JP 2428480A JP 2428480 A JP2428480 A JP 2428480A JP S56120224 A JPS56120224 A JP S56120224A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- latch
- circuit
- type counter
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
Landscapes
- Electronic Switches (AREA)
Abstract
PURPOSE:To avoid the change in the circuit even with the increase/decrease in the number of digits for the coincidence circuit of the time sharing type counter, by giving a clock signal to the 1st latch circuit and giving the set signal to the 1st and 2nd lach circuits. CONSTITUTION:While the set signal S is at H level, the content counted at the counters A, B are outputted to a comparator C every digit sequentially with the signal fed to number of digit set terminals K0-K3. The comparator C compares the content of the counters A, B each digit, and if in coincidence, the signal of H level is outputted to an AND circuit AND and if in uncoincidence, the signal of L level, and it is applied to the data input terminal D of a latch M1. Clock signals D0-D3 are applied to a storbe terminal of the latch M1, the output of the latch M1 is applied to the data input terminal of the latch M2, and the set pignal is applied to the strobe terminal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2428480A JPS56120224A (en) | 1980-02-28 | 1980-02-28 | Coincidence circuit for time sharing type counter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2428480A JPS56120224A (en) | 1980-02-28 | 1980-02-28 | Coincidence circuit for time sharing type counter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56120224A true JPS56120224A (en) | 1981-09-21 |
Family
ID=12133878
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2428480A Pending JPS56120224A (en) | 1980-02-28 | 1980-02-28 | Coincidence circuit for time sharing type counter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56120224A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62156732A (en) * | 1985-12-27 | 1987-07-11 | Nec Corp | Counter circuit |
JPS638823A (en) * | 1986-06-27 | 1988-01-14 | Ando Electric Co Ltd | Continuous data detecting circuit |
US5134384A (en) * | 1989-03-02 | 1992-07-28 | Oki Electric Industry Co., Ltd. | Data coincidence detecting circuit |
-
1980
- 1980-02-28 JP JP2428480A patent/JPS56120224A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62156732A (en) * | 1985-12-27 | 1987-07-11 | Nec Corp | Counter circuit |
JPS638823A (en) * | 1986-06-27 | 1988-01-14 | Ando Electric Co Ltd | Continuous data detecting circuit |
US5134384A (en) * | 1989-03-02 | 1992-07-28 | Oki Electric Industry Co., Ltd. | Data coincidence detecting circuit |
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