JPS57121270A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57121270A
JPS57121270A JP637281A JP637281A JPS57121270A JP S57121270 A JPS57121270 A JP S57121270A JP 637281 A JP637281 A JP 637281A JP 637281 A JP637281 A JP 637281A JP S57121270 A JPS57121270 A JP S57121270A
Authority
JP
Japan
Prior art keywords
mosfet
clamping
charge
pad
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP637281A
Other languages
Japanese (ja)
Inventor
Satoshi Meguro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP637281A priority Critical patent/JPS57121270A/en
Publication of JPS57121270A publication Critical patent/JPS57121270A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain sufficient electrostatic destruction resistance of a semiconductor device by providing an MISFET between a clamping resistor and a pad, discharging the charge through the FET, and reducing the area of a clamping diode. CONSTITUTION:A parasitic MOSFET 5 is arranged between the pad 2 and the clamping resistor 4 in a region of approximately equal in potential to a bonding pad 2, a high voltage is applied to between the gate and drain 6 of the MOSFET 5 in the amount corresponding to the potential difference produced across the clamping resistor 4, and the field oxidized film 15 of the MOSFET can be inverted to an N type. Accordingly, the MOSFET becomes ON state due to the induction of the channel, and the charge at the clamping diode 3 side is discharged through an aluminum wire 14, the channel of the MOSFET and a wire 13. In this manner, the charge can be effectively discharged by controlling the threshold voltage of the MOSFET, thereby increasing the electrostatic destruction resistance of the diode.
JP637281A 1981-01-21 1981-01-21 Semiconductor device Pending JPS57121270A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP637281A JPS57121270A (en) 1981-01-21 1981-01-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP637281A JPS57121270A (en) 1981-01-21 1981-01-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS57121270A true JPS57121270A (en) 1982-07-28

Family

ID=11636533

Family Applications (1)

Application Number Title Priority Date Filing Date
JP637281A Pending JPS57121270A (en) 1981-01-21 1981-01-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57121270A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0106417A2 (en) * 1982-10-20 1984-04-25 Koninklijke Philips Electronics N.V. Integrated circuit comprising an input protection device
JPS6173427A (en) * 1984-09-18 1986-04-15 Matsushita Electric Ind Co Ltd Amplifier circuit for fm intermediate frequency
KR100506970B1 (en) * 1998-09-01 2005-10-26 삼성전자주식회사 Electrostatic Discharge Prevention Semiconductor Device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0106417A2 (en) * 1982-10-20 1984-04-25 Koninklijke Philips Electronics N.V. Integrated circuit comprising an input protection device
JPS6173427A (en) * 1984-09-18 1986-04-15 Matsushita Electric Ind Co Ltd Amplifier circuit for fm intermediate frequency
KR100506970B1 (en) * 1998-09-01 2005-10-26 삼성전자주식회사 Electrostatic Discharge Prevention Semiconductor Device

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