JPS57114941A - Multiplication circuit - Google Patents

Multiplication circuit

Info

Publication number
JPS57114941A
JPS57114941A JP56000619A JP61981A JPS57114941A JP S57114941 A JPS57114941 A JP S57114941A JP 56000619 A JP56000619 A JP 56000619A JP 61981 A JP61981 A JP 61981A JP S57114941 A JPS57114941 A JP S57114941A
Authority
JP
Japan
Prior art keywords
subtractor
adder
sws
output
phi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56000619A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6161410B2 (enExample
Inventor
Hiroshi Mobara
Norishige Tanaka
Yukihiro Saeki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56000619A priority Critical patent/JPS57114941A/ja
Publication of JPS57114941A publication Critical patent/JPS57114941A/ja
Publication of JPS6161410B2 publication Critical patent/JPS6161410B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
JP56000619A 1981-01-06 1981-01-06 Multiplication circuit Granted JPS57114941A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56000619A JPS57114941A (en) 1981-01-06 1981-01-06 Multiplication circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56000619A JPS57114941A (en) 1981-01-06 1981-01-06 Multiplication circuit

Publications (2)

Publication Number Publication Date
JPS57114941A true JPS57114941A (en) 1982-07-17
JPS6161410B2 JPS6161410B2 (enExample) 1986-12-25

Family

ID=11478738

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56000619A Granted JPS57114941A (en) 1981-01-06 1981-01-06 Multiplication circuit

Country Status (1)

Country Link
JP (1) JPS57114941A (enExample)

Also Published As

Publication number Publication date
JPS6161410B2 (enExample) 1986-12-25

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