JPS57114283A - Non-volatile semiconductive memory - Google Patents

Non-volatile semiconductive memory

Info

Publication number
JPS57114283A
JPS57114283A JP135781A JP135781A JPS57114283A JP S57114283 A JPS57114283 A JP S57114283A JP 135781 A JP135781 A JP 135781A JP 135781 A JP135781 A JP 135781A JP S57114283 A JPS57114283 A JP S57114283A
Authority
JP
Japan
Prior art keywords
drain
source
mos transistor
regions
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP135781A
Other languages
Japanese (ja)
Other versions
JPH0127587B2 (en
Inventor
Hiroshi Iwahashi
Hiroshi Harada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP135781A priority Critical patent/JPS57114283A/en
Publication of JPS57114283A publication Critical patent/JPS57114283A/en
Publication of JPH0127587B2 publication Critical patent/JPH0127587B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components

Abstract

PURPOSE:To improve the data reading speed of a non-volatile semiconductor memory and to form ultrafine element by forming transistors for a memory cell and peripheral circuit in separated another semiconductor regions. CONSTITUTION:Two p-type well regions 12, 13 are isolated and formed in the surface region of a substrate 11. A pair of n<+>type regions 14, 15 becoming the drain and the source of an MOS transistor are formed at the prescribed interval on the surface region of one 12 of the well regions. A floating gate 16 and a control gate 17 form a double gate type MOS transistor with drain, source to become a memory cell. A pair of n<+>type regions 18, 19 becoming the drain and the source of an MOS transistor are formed at the prescribed interval on the surface region of the other 13 of the well regions. A gate 20 forms an MOS transistor with drain, source and peripheral circuit.
JP135781A 1981-01-08 1981-01-08 Non-volatile semiconductive memory Granted JPS57114283A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP135781A JPS57114283A (en) 1981-01-08 1981-01-08 Non-volatile semiconductive memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP135781A JPS57114283A (en) 1981-01-08 1981-01-08 Non-volatile semiconductive memory

Publications (2)

Publication Number Publication Date
JPS57114283A true JPS57114283A (en) 1982-07-16
JPH0127587B2 JPH0127587B2 (en) 1989-05-30

Family

ID=11499241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP135781A Granted JPS57114283A (en) 1981-01-08 1981-01-08 Non-volatile semiconductive memory

Country Status (1)

Country Link
JP (1) JPS57114283A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55156370A (en) * 1979-05-25 1980-12-05 Hitachi Ltd Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55156370A (en) * 1979-05-25 1980-12-05 Hitachi Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPH0127587B2 (en) 1989-05-30

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