JPS57113649A - Signal encryption device - Google Patents
Signal encryption deviceInfo
- Publication number
- JPS57113649A JPS57113649A JP55186243A JP18624380A JPS57113649A JP S57113649 A JPS57113649 A JP S57113649A JP 55186243 A JP55186243 A JP 55186243A JP 18624380 A JP18624380 A JP 18624380A JP S57113649 A JPS57113649 A JP S57113649A
- Authority
- JP
- Japan
- Prior art keywords
- words
- ram6
- address
- counter
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04K—SECRET COMMUNICATION; JAMMING OF COMMUNICATION
- H04K1/00—Secret communication
- H04K1/06—Secret communication by transmitting the information or elements thereof at unnatural speeds or in jumbled order or backwards
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
Abstract
PURPOSE:To make encryption, by sectioing signals into packets on a time axis and inverting the time axis of signals in each packet. CONSTITUTION:An audio signal from a microphone 1 or input terminal 2 is applied to an AD converter 5 via an amplifier 3, Nyquist filter 4, converted into digital words time by time, and stored in an RAM6. The address stored in the RAM6 is specified by a counter 13, the signal sample words are contained in order from lower to upper addresses in the RAM6, and the signal returns to the lowermost address 0 due to the overflow of the counter 13 and new words are written in while destroying the signal words contained before. The address words given from the counter 13 are inverted for each bit with an exclusive logical sum gate group 11 according to the logical value of a clock phi0, or selected as they are and given to the RAM6. The scanning direction of address is inverted at write-in readout with the operation of the group 11.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55186243A JPS57113649A (en) | 1980-12-30 | 1980-12-30 | Signal encryption device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55186243A JPS57113649A (en) | 1980-12-30 | 1980-12-30 | Signal encryption device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57113649A true JPS57113649A (en) | 1982-07-15 |
Family
ID=16184849
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55186243A Pending JPS57113649A (en) | 1980-12-30 | 1980-12-30 | Signal encryption device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57113649A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5947886A (en) * | 1982-09-10 | 1984-03-17 | Hitachi Ltd | Scramble system |
-
1980
- 1980-12-30 JP JP55186243A patent/JPS57113649A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5947886A (en) * | 1982-09-10 | 1984-03-17 | Hitachi Ltd | Scramble system |
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