JPS56164441A - Addition and substraction device for pcm signal - Google Patents

Addition and substraction device for pcm signal

Info

Publication number
JPS56164441A
JPS56164441A JP6640680A JP6640680A JPS56164441A JP S56164441 A JPS56164441 A JP S56164441A JP 6640680 A JP6640680 A JP 6640680A JP 6640680 A JP6640680 A JP 6640680A JP S56164441 A JPS56164441 A JP S56164441A
Authority
JP
Japan
Prior art keywords
memory
addition
memories
pcm signal
address information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6640680A
Other languages
Japanese (ja)
Inventor
Yasushi Wakahara
Yoshikazu Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KDDI Corp
Original Assignee
Kokusai Denshin Denwa KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kokusai Denshin Denwa KK filed Critical Kokusai Denshin Denwa KK
Priority to JP6640680A priority Critical patent/JPS56164441A/en
Priority to GB8030171A priority patent/GB2059123B/en
Priority to US06/189,539 priority patent/US4357674A/en
Publication of JPS56164441A publication Critical patent/JPS56164441A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/49—Computations with a radix, other than binary, 8, 16 or decimal, e.g. ternary, negative or imaginary radices, mixed radix non-linear PCM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B14/00—Transmission systems not characterised by the medium used for transmission
    • H04B14/02—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
    • H04B14/04—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using pulse code modulation
    • H04B14/046—Systems or methods for reducing noise or bandwidth
    • H04B14/048—Non linear compression or expansion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges
    • H04M3/42—Systems providing special services or facilities to subscribers
    • H04M3/56—Arrangements for connecting several subscribers to a common circuit, i.e. affording conference facilities
    • H04M3/561—Arrangements for connecting several subscribers to a common circuit, i.e. affording conference facilities by multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Multimedia (AREA)
  • General Engineering & Computer Science (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)

Abstract

PURPOSE:To make possible high speed operation, by making addition with PCM signals eliminated polarity bits and making subtraction with the addition of PCM signals for addition and subtractor after inverting the polarity bits. CONSTITUTION:Segment bits in an input PCM signal are address information of a memory 280. On the other hand, a step bit of the PCM signal is the address information for memories 350, 360, after being added with the output of gates 29, 30 and the information of result of readout of the memory 280. The memories 350, 360 output a mantissa bit completing the digit alignment of the shift register. The result of readout of the memories 350, 360 is the address information of a memory 370, and subtraction is executed by reading out this memory. That is, the memory 370 has a function of two elements, a subtractor 37 and a logical circuit 38.
JP6640680A 1979-09-22 1980-05-21 Addition and substraction device for pcm signal Pending JPS56164441A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP6640680A JPS56164441A (en) 1980-05-21 1980-05-21 Addition and substraction device for pcm signal
GB8030171A GB2059123B (en) 1979-09-22 1980-09-18 Pcm signal calculator
US06/189,539 US4357674A (en) 1979-09-22 1980-09-22 PCM Signal calculator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6640680A JPS56164441A (en) 1980-05-21 1980-05-21 Addition and substraction device for pcm signal

Publications (1)

Publication Number Publication Date
JPS56164441A true JPS56164441A (en) 1981-12-17

Family

ID=13314879

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6640680A Pending JPS56164441A (en) 1979-09-22 1980-05-21 Addition and substraction device for pcm signal

Country Status (1)

Country Link
JP (1) JPS56164441A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4698771A (en) * 1984-12-31 1987-10-06 Gte Communication Systems Corporation Adder circuit for encoded PCM samples

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4698771A (en) * 1984-12-31 1987-10-06 Gte Communication Systems Corporation Adder circuit for encoded PCM samples

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