JPS5710859A - Interprocessor communication system - Google Patents
Interprocessor communication systemInfo
- Publication number
- JPS5710859A JPS5710859A JP8537580A JP8537580A JPS5710859A JP S5710859 A JPS5710859 A JP S5710859A JP 8537580 A JP8537580 A JP 8537580A JP 8537580 A JP8537580 A JP 8537580A JP S5710859 A JPS5710859 A JP S5710859A
- Authority
- JP
- Japan
- Prior art keywords
- data
- error
- correctness
- received
- sent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
Abstract
PURPOSE:To execute a logical error inspection of a data to be communicated, by a sending side, by providing a correctness and error informaton data part for informing whether a data which has been sent in the previous time is correct or erroneous, in a sending data. CONSTITUTION:When inspecting the rationality of a data to be communicated in an interprocessor communication, its partial logical error inspection is executed in a sending side, and in a sending data is provided a correctness and error information data part for information whether a data which has been sent previous time is correct or erroneous, through which it is sent. A signal from a data bus 106 is received by a receiving device 113, a received data is stored in a buffer 204, also contents of a register 202 in which a correctness or error decision data of a data which has been received in the previous time has been registered, and a correctness and error information data which has been received this time are detected by a coincidence detecting circuit 201, and a logical circuit 203 sends out a confirmation signal 208 to a receiving processor 110.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8537580A JPS5710859A (en) | 1980-06-24 | 1980-06-24 | Interprocessor communication system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8537580A JPS5710859A (en) | 1980-06-24 | 1980-06-24 | Interprocessor communication system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5710859A true JPS5710859A (en) | 1982-01-20 |
Family
ID=13856966
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8537580A Pending JPS5710859A (en) | 1980-06-24 | 1980-06-24 | Interprocessor communication system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5710859A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8776782B2 (en) * | 2009-04-27 | 2014-07-15 | Kingspan Holdings (Irl) Limited | Solar collector |
-
1980
- 1980-06-24 JP JP8537580A patent/JPS5710859A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8776782B2 (en) * | 2009-04-27 | 2014-07-15 | Kingspan Holdings (Irl) Limited | Solar collector |
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