JPS57107653A - Reception timing pickup system - Google Patents

Reception timing pickup system

Info

Publication number
JPS57107653A
JPS57107653A JP55183609A JP18360980A JPS57107653A JP S57107653 A JPS57107653 A JP S57107653A JP 55183609 A JP55183609 A JP 55183609A JP 18360980 A JP18360980 A JP 18360980A JP S57107653 A JPS57107653 A JP S57107653A
Authority
JP
Japan
Prior art keywords
output
circuit
filter
peak value
reception timing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55183609A
Other languages
Japanese (ja)
Other versions
JPS6058622B2 (en
Inventor
Takashi Kaku
Shigeyuki Umigami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55183609A priority Critical patent/JPS6058622B2/en
Publication of JPS57107653A publication Critical patent/JPS57107653A/en
Publication of JPS6058622B2 publication Critical patent/JPS6058622B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To obtain a timing output with constant amplitude, by obtaining a peak value of output waveform of a timing filter and multiplicating the reciprocal of the peak value with an output waveform. CONSTITUTION:A reception timing signal is reproduced at a filter 4 via an automatic gain control circuit AGC1, sample hold circuit S/H2, and A/D converter 3. The output of the filter 4 is inputted to a multiplication section 13 and a reciprocal operation circuit 11. After the output 1/A(where; A is peak value) of the circuit 11 is averaged at an average value circuit 12 so that it is not subject to noise, the output is inputted to a multiplication section 13. Thus, the timing signal in which the amplitude is normallized to 1 can be obtained.
JP55183609A 1980-12-24 1980-12-24 Reception timing extraction method Expired JPS6058622B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55183609A JPS6058622B2 (en) 1980-12-24 1980-12-24 Reception timing extraction method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55183609A JPS6058622B2 (en) 1980-12-24 1980-12-24 Reception timing extraction method

Publications (2)

Publication Number Publication Date
JPS57107653A true JPS57107653A (en) 1982-07-05
JPS6058622B2 JPS6058622B2 (en) 1985-12-20

Family

ID=16138785

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55183609A Expired JPS6058622B2 (en) 1980-12-24 1980-12-24 Reception timing extraction method

Country Status (1)

Country Link
JP (1) JPS6058622B2 (en)

Also Published As

Publication number Publication date
JPS6058622B2 (en) 1985-12-20

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