JPS57107037A - Method for flattening silicon dioxide - Google Patents

Method for flattening silicon dioxide

Info

Publication number
JPS57107037A
JPS57107037A JP56137887A JP13788781A JPS57107037A JP S57107037 A JPS57107037 A JP S57107037A JP 56137887 A JP56137887 A JP 56137887A JP 13788781 A JP13788781 A JP 13788781A JP S57107037 A JPS57107037 A JP S57107037A
Authority
JP
Japan
Prior art keywords
silicon dioxide
flattening
flattening silicon
dioxide
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56137887A
Other languages
English (en)
Japanese (ja)
Other versions
JPS637458B2 (https=
Inventor
Jii Anansa Narashipaa
Esu Baateia Haasaran
Esu Rekaton Jiyon
Eru Uorushiyu Jieemuzu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS57107037A publication Critical patent/JPS57107037A/ja
Publication of JPS637458B2 publication Critical patent/JPS637458B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
    • H10P95/062—Planarisation of inorganic insulating materials involving a dielectric removal step
    • H10P95/064—Planarisation of inorganic insulating materials involving a dielectric removal step the removal being chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/68—Organic materials, e.g. photoresists
    • H10P14/683—Organic materials, e.g. photoresists carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means

Landscapes

  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)
  • Silicon Compounds (AREA)
JP56137887A 1980-12-16 1981-09-03 Method for flattening silicon dioxide Granted JPS57107037A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/217,077 US4389281A (en) 1980-12-16 1980-12-16 Method of planarizing silicon dioxide in semiconductor devices

Publications (2)

Publication Number Publication Date
JPS57107037A true JPS57107037A (en) 1982-07-03
JPS637458B2 JPS637458B2 (https=) 1988-02-17

Family

ID=22809590

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56137887A Granted JPS57107037A (en) 1980-12-16 1981-09-03 Method for flattening silicon dioxide

Country Status (4)

Country Link
US (1) US4389281A (https=)
EP (1) EP0054164B1 (https=)
JP (1) JPS57107037A (https=)
DE (1) DE3162991D1 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08250486A (ja) * 1996-03-08 1996-09-27 Semiconductor Energy Lab Co Ltd 半導体装置
JPH1064993A (ja) * 1996-06-27 1998-03-06 Hyundai Electron Ind Co Ltd 素子分離構造を有する半導体装置とその製造方法
WO2023282131A1 (ja) * 2021-07-08 2023-01-12 東京エレクトロン株式会社 エッチング方法

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4576900A (en) * 1981-10-09 1986-03-18 Amdahl Corporation Integrated circuit multilevel interconnect system and method
US4511430A (en) * 1984-01-30 1985-04-16 International Business Machines Corporation Control of etch rate ratio of SiO2 /photoresist for quartz planarization etch back process
JPS60214532A (ja) * 1984-04-11 1985-10-26 Nippon Telegr & Teleph Corp <Ntt> パタ−ン形成方法
US4583282A (en) * 1984-09-14 1986-04-22 Motorola, Inc. Process for self-aligned buried layer, field guard, and isolation
US4574469A (en) * 1984-09-14 1986-03-11 Motorola, Inc. Process for self-aligned buried layer, channel-stop, and isolation
USH204H (en) 1984-11-29 1987-02-03 At&T Bell Laboratories Method for implanting the sidewalls of isolation trenches
JPS61144639A (ja) * 1984-12-19 1986-07-02 Hitachi Ltd 放射線感応性組成物及びそれを用いたパタ−ン形成法
US4662986A (en) * 1985-06-27 1987-05-05 Signetics Corporation Planarization method and technique for isolating semiconductor islands
US4655874A (en) * 1985-07-26 1987-04-07 Advanced Micro Devices, Inc. Process for smoothing a non-planar surface
US4665007A (en) * 1985-08-19 1987-05-12 International Business Machines Corporation Planarization process for organic filling of deep trenches
US4749440A (en) * 1985-08-28 1988-06-07 Fsi Corporation Gaseous process and apparatus for removing films from substrates
US4654120A (en) * 1985-10-31 1987-03-31 International Business Machines Corporation Method of making a planar trench semiconductor structure
US5324536A (en) * 1986-04-28 1994-06-28 Canon Kabushiki Kaisha Method of forming a multilayered structure
JPS6377122A (ja) * 1986-09-19 1988-04-07 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
DE3877121D1 (de) * 1987-10-23 1993-02-11 Siemens Ag Verfahren zur herstellung eines planaren selbstjustierten heterobipolartransistors.
US4836885A (en) * 1988-05-03 1989-06-06 International Business Machines Corporation Planarization process for wide trench isolation
JPH02167671A (ja) * 1988-12-21 1990-06-28 Disco Abrasive Syst Ltd カーボン入り電着砥石
JPH04223876A (ja) * 1990-12-26 1992-08-13 Mitsubishi Materials Corp レンズ研削用砥石
DE4239075C1 (de) * 1992-11-20 1994-04-07 Itt Ind Gmbh Deutsche Verfahren zur globalen Planarisierung von Oberflächen integrierter Halbleiterschaltungen
US5275973A (en) * 1993-03-01 1994-01-04 Motorola, Inc. Method for forming metallization in an integrated circuit
JP3072876B2 (ja) * 1993-09-17 2000-08-07 日曹エンジニアリング株式会社 エッチング液の精製方法
US7323417B2 (en) * 2004-09-21 2008-01-29 Molecular Imprints, Inc. Method of forming a recessed structure employing a reverse tone process
US7205244B2 (en) * 2004-09-21 2007-04-17 Molecular Imprints Patterning substrates employing multi-film layers defining etch-differential interfaces
US7547504B2 (en) * 2004-09-21 2009-06-16 Molecular Imprints, Inc. Pattern reversal employing thick residual layers
US20070077763A1 (en) * 2005-09-30 2007-04-05 Molecular Imprints, Inc. Deposition technique to planarize a multi-layer structure
JP4645492B2 (ja) * 2006-03-17 2011-03-09 セイコーエプソン株式会社 金属パターン形成方法
JP2009302222A (ja) * 2008-06-12 2009-12-24 Sanyo Electric Co Ltd メサ型半導体装置及びその製造方法
JP2010021532A (ja) * 2008-06-12 2010-01-28 Sanyo Electric Co Ltd メサ型半導体装置及びその製造方法
US10879108B2 (en) * 2016-11-15 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Topographic planarization method for lithography process

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3976524A (en) * 1974-06-17 1976-08-24 Ibm Corporation Planarization of integrated circuit surfaces through selective photoresist masking
GB1539700A (en) * 1976-05-14 1979-01-31 Int Plasma Corp Process for etching sio2
JPS5456985A (en) * 1977-10-14 1979-05-08 Mitsubishi Chem Ind Ltd Gas-separaing membrane
US4307179A (en) * 1980-07-03 1981-12-22 International Business Machines Corporation Planar metal interconnection system and process

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08250486A (ja) * 1996-03-08 1996-09-27 Semiconductor Energy Lab Co Ltd 半導体装置
JPH1064993A (ja) * 1996-06-27 1998-03-06 Hyundai Electron Ind Co Ltd 素子分離構造を有する半導体装置とその製造方法
US5904541A (en) * 1996-06-27 1999-05-18 Hyundai Electronics Industries Co., Ltd. Method for fabricating a semiconductor device having a shallow trench isolation structure
WO2023282131A1 (ja) * 2021-07-08 2023-01-12 東京エレクトロン株式会社 エッチング方法

Also Published As

Publication number Publication date
EP0054164A1 (en) 1982-06-23
US4389281A (en) 1983-06-21
EP0054164B1 (en) 1984-04-04
JPS637458B2 (https=) 1988-02-17
DE3162991D1 (en) 1984-05-10

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