JPS57103180A - Cash memory control system - Google Patents

Cash memory control system

Info

Publication number
JPS57103180A
JPS57103180A JP55179851A JP17985180A JPS57103180A JP S57103180 A JPS57103180 A JP S57103180A JP 55179851 A JP55179851 A JP 55179851A JP 17985180 A JP17985180 A JP 17985180A JP S57103180 A JPS57103180 A JP S57103180A
Authority
JP
Japan
Prior art keywords
memory
cash memory
cash
data
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55179851A
Other languages
Japanese (ja)
Inventor
Tomohito Shibata
Masaaki Kobayashi
Shigeru Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55179851A priority Critical patent/JPS57103180A/en
Publication of JPS57103180A publication Critical patent/JPS57103180A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing

Abstract

PURPOSE:To eliminate the need for the V-bit part of a cash memory by storing a effective signal for the contents of the cash memory temporarily, and by discriminating the contents effective signal. CONSTITUTION:A control part 6 reads and executes a routine program R in a memory 2, and writes addresses and data, read out of the memory 2, in the address part A and data part D of a cash memory 4. Once the writing operation ends, the control part 6 sends a control signal B to set an FF7. A discriminating circuit 3 compares a memory address M and a cash memory address L with each other to make a decision and, when confirming that the output signal of the FF7 is 1, sends a control signal C. Therefore, a readout control circuit 5 reads data (d) out of the cash memory 4.
JP55179851A 1980-12-19 1980-12-19 Cash memory control system Pending JPS57103180A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55179851A JPS57103180A (en) 1980-12-19 1980-12-19 Cash memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55179851A JPS57103180A (en) 1980-12-19 1980-12-19 Cash memory control system

Publications (1)

Publication Number Publication Date
JPS57103180A true JPS57103180A (en) 1982-06-26

Family

ID=16073016

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55179851A Pending JPS57103180A (en) 1980-12-19 1980-12-19 Cash memory control system

Country Status (1)

Country Link
JP (1) JPS57103180A (en)

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