JPS5757356A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS5757356A
JPS5757356A JP55132006A JP13200680A JPS5757356A JP S5757356 A JPS5757356 A JP S5757356A JP 55132006 A JP55132006 A JP 55132006A JP 13200680 A JP13200680 A JP 13200680A JP S5757356 A JPS5757356 A JP S5757356A
Authority
JP
Japan
Prior art keywords
flag
external storage
processor
register
data processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55132006A
Other languages
Japanese (ja)
Inventor
Koichi Igari
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55132006A priority Critical patent/JPS5757356A/en
Publication of JPS5757356A publication Critical patent/JPS5757356A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To increase the processing capacity of a processor, by setting a flag correponding to a renewal writing address on an external storage controller having a cash buffer and reporting the flag between two external storage controllers. CONSTITUTION:Flag registers 15 and 15' plus a transfer circuit 18 are added to external storage controllers 3 and 4 having a cash buffer 13 respectively. Then the flag provided to each block is set to the register 15 when a storage renewal writing is register 15' of the controller 4 is read to discriminate that the renewal writing is carried out. In such way, the storage control of a cash buffer is carried out between the external storage controllers independently of a processor, so that the processing capacity is increased for processor.
JP55132006A 1980-09-22 1980-09-22 Data processing system Pending JPS5757356A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55132006A JPS5757356A (en) 1980-09-22 1980-09-22 Data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55132006A JPS5757356A (en) 1980-09-22 1980-09-22 Data processing system

Publications (1)

Publication Number Publication Date
JPS5757356A true JPS5757356A (en) 1982-04-06

Family

ID=15071338

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55132006A Pending JPS5757356A (en) 1980-09-22 1980-09-22 Data processing system

Country Status (1)

Country Link
JP (1) JPS5757356A (en)

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