JPS5694668A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5694668A
JPS5694668A JP17166979A JP17166979A JPS5694668A JP S5694668 A JPS5694668 A JP S5694668A JP 17166979 A JP17166979 A JP 17166979A JP 17166979 A JP17166979 A JP 17166979A JP S5694668 A JPS5694668 A JP S5694668A
Authority
JP
Japan
Prior art keywords
film
metal
metal silicide
electrode pattern
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17166979A
Other languages
Japanese (ja)
Inventor
Yukio Omori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP17166979A priority Critical patent/JPS5694668A/en
Publication of JPS5694668A publication Critical patent/JPS5694668A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32105—Oxidation of silicon-containing layers

Abstract

PURPOSE:To prevent the extraction of metal from a silicide and thereby enhance the reliability of IC by connecting a polycrystalline Si film to the exposed surface of the metal silicide, applying heat treatment thereto to change the same into an SiO2 film, and thereby covering the metal silicide. CONSTITUTION:The SiO2 film 12 is connected to the surface of the Si substrate 11 and further the metal silicide 13 such as WSi2, MoSi2 and PtSi2 is connected on to the film 12, wherefrom a gate electrode pattern is formed through photoetching. Next, the polycrystalline Si layer 14 is connected uniformly to the exposed surface of the electrode pattern 13 by the CVD method and is changed, by heat treatment, into the SiO2 film 15, whereby the gate electrode pattern 13 is completely surrounded. In this way, no metal is extracted from the metal silicide 13, thereby the unevenness of the surface is eliminated, and thus the semiconductor device having high integration and high speed of operation can be obtained.
JP17166979A 1979-12-27 1979-12-27 Manufacture of semiconductor device Pending JPS5694668A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17166979A JPS5694668A (en) 1979-12-27 1979-12-27 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17166979A JPS5694668A (en) 1979-12-27 1979-12-27 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5694668A true JPS5694668A (en) 1981-07-31

Family

ID=15927490

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17166979A Pending JPS5694668A (en) 1979-12-27 1979-12-27 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5694668A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5654242A (en) * 1994-09-28 1997-08-05 Sony Corporation Method for making refractory metal silicide electrode

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5654242A (en) * 1994-09-28 1997-08-05 Sony Corporation Method for making refractory metal silicide electrode

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