JPS5681927A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5681927A
JPS5681927A JP15956879A JP15956879A JPS5681927A JP S5681927 A JPS5681927 A JP S5681927A JP 15956879 A JP15956879 A JP 15956879A JP 15956879 A JP15956879 A JP 15956879A JP S5681927 A JPS5681927 A JP S5681927A
Authority
JP
Japan
Prior art keywords
reaction tube
layer
torr
unified
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15956879A
Other languages
Japanese (ja)
Other versions
JPH0120528B2 (en
Inventor
Hideaki Matsubara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP15956879A priority Critical patent/JPS5681927A/en
Publication of JPS5681927A publication Critical patent/JPS5681927A/en
Publication of JPH0120528B2 publication Critical patent/JPH0120528B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)

Abstract

PURPOSE:To obtain a unified diffusion layer by a method wherein an impurity gas is made to flow while a decompression state is retained in a reaction tube and after a molding, a unified impurity evaporation layer is introduced and diffused efficiently. CONSTITUTION:After temperature is set at 1,000 deg.C in a furnace and air is withdrawn upto 3 Torr in a reaction tube 3, a given quantity of PH3, N2, O2 is made to flow every minute and P is evaporated on an Si wafer while the value of 3 Torr is retained by adjusting a valve. Next thereto, PH3 is removed and the temperature of the furnace is set to 1,100 deg.C and then, a thermal processing is performed and an N layer is formed by means of the diffusion of P. With this constitution, since the evaporation of P is performed gradually under a decompression state, a generation of a defect and distortion on the surface is sharply decreased, contamination of a reaction tube, a boat and a wafer is reduced, thereby, improving a yield.
JP15956879A 1979-12-07 1979-12-07 Manufacture of semiconductor device Granted JPS5681927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15956879A JPS5681927A (en) 1979-12-07 1979-12-07 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15956879A JPS5681927A (en) 1979-12-07 1979-12-07 Manufacture of semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP5094581A Division JPS56162830A (en) 1981-04-03 1981-04-03 Impurity depositing and diffusing device

Publications (2)

Publication Number Publication Date
JPS5681927A true JPS5681927A (en) 1981-07-04
JPH0120528B2 JPH0120528B2 (en) 1989-04-17

Family

ID=15696559

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15956879A Granted JPS5681927A (en) 1979-12-07 1979-12-07 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5681927A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5068052A (en) * 1973-10-17 1975-06-07
JPS5468052A (en) * 1977-11-08 1979-05-31 Nippon Kankou Shikiso Kenkiyuu Method of eliminating harmful used waste liquid of oxidant meter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5068052A (en) * 1973-10-17 1975-06-07
JPS5468052A (en) * 1977-11-08 1979-05-31 Nippon Kankou Shikiso Kenkiyuu Method of eliminating harmful used waste liquid of oxidant meter

Also Published As

Publication number Publication date
JPH0120528B2 (en) 1989-04-17

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