JPH0120528B2 - - Google Patents
Info
- Publication number
- JPH0120528B2 JPH0120528B2 JP54159568A JP15956879A JPH0120528B2 JP H0120528 B2 JPH0120528 B2 JP H0120528B2 JP 54159568 A JP54159568 A JP 54159568A JP 15956879 A JP15956879 A JP 15956879A JP H0120528 B2 JPH0120528 B2 JP H0120528B2
- Authority
- JP
- Japan
- Prior art keywords
- impurity
- gas
- temperature
- semiconductor substrate
- impurity diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000012535 impurity Substances 0.000 claims description 33
- 238000009792 diffusion process Methods 0.000 claims description 24
- 239000007789 gas Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000007740 vapor deposition Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 239000011261 inert gas Substances 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 25
- 230000007547 defect Effects 0.000 description 3
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Description
【発明の詳細な説明】
本発明は、半導体基板（以下ウエハと称す）上
に濃度の均一な不純物拡散層を選択的に形成する
方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for selectively forming an impurity diffusion layer with a uniform concentration on a semiconductor substrate (hereinafter referred to as a wafer).
熱拡散法を用いて不純物拡散層を形成するにあ
たり、通常、拡散炉内に設置された反応管内に、
不純物拡散用のマスクが形成されたウエハを配置
し、不純物ガスを流すことにより前記ウエハ上に
不純物蒸着層を形成したのちウエハ内に拡散する
方法がとられている。 When forming an impurity diffusion layer using the thermal diffusion method, usually a reaction tube installed in a diffusion furnace is
A method is used in which a wafer on which a mask for impurity diffusion is formed is placed, and an impurity vapor deposition layer is formed on the wafer by flowing an impurity gas, and then the impurity is diffused into the wafer.
この場合、再現性よく均一な不純物拡散層を得
るには、ウエハ全面にわたつて均一な不純物蒸着
層が形成されなければならない。不純物蒸着量の
制御は通常ガス流量、温度、時間の調整によつて
なされているが、この方法では、上記の目的の達
成はできず、形成される不純物蒸着層の厚さにつ
いてウエハ内、ウエハ間、ロツト間でのばらつき
が大きく、ウエハの載置方法や大きさ処理枚数に
制限があり、同時に多数枚のウエハに対して均一
な蒸着層を形成することは困難であつた。強い
て、均一な不純物拡散層を得るには高濃度の不純
物拡散層を必要とし、高濃度では表面欠陥を発生
し易いため、たとえば低雑音トランジスタのエミ
ツタ領域形成等には適用できない欠点があつた。 In this case, in order to obtain a uniform impurity diffusion layer with good reproducibility, a uniform impurity vapor deposition layer must be formed over the entire surface of the wafer. The amount of impurity evaporated is usually controlled by adjusting the gas flow rate, temperature, and time, but this method cannot achieve the above objectives, and the thickness of the impurity evaporated layer formed cannot be controlled within the wafer or on the wafer. There are large variations between wafers and lots, and there are restrictions on the mounting method and size of wafers and the number of wafers that can be processed, making it difficult to form a uniform vapor deposition layer on a large number of wafers at the same time. However, in order to obtain a uniform impurity diffusion layer, a high concentration impurity diffusion layer is required, and a high concentration tends to cause surface defects, so it has the drawback that it cannot be applied to, for example, the formation of an emitter region of a low noise transistor.
本発明はこれらの欠点に鑑みてなされたもので
反応管内を減圧状態に保ちつつ不純物ガスを流
し、均一な不純物蒸着層を作業性良く形成したの
ち、これを導入拡散させ均一な不純物拡散層を得
ようとするものである。 The present invention was developed in view of these drawbacks, and involves flowing an impurity gas while keeping the inside of the reaction tube in a reduced pressure state to form a uniform impurity vapor deposition layer with good workability, and then introducing and diffusing this to form a uniform impurity diffusion layer. That's what you're trying to get.
次に、図面を参照しつつ本発明を説明する。第
１図に示すように本発明の製造方法で使用する蒸
着拡散装置は、炉１内に設置された反応管２の一
端がガス供給系３に、他端が圧力コントロールバ
ルブ４を介して真空排気系５に接続された構造を
有しており、シリコンウエハ６は反応管内に、管
軸方向に対して垂直となるように立てて30枚配置
される。ここで７はトラツプ、８は真空計であ
る。 Next, the present invention will be explained with reference to the drawings. As shown in FIG. 1, the vapor deposition diffusion apparatus used in the manufacturing method of the present invention has one end of a reaction tube 2 installed in a furnace 1 connected to a gas supply system 3, and the other end connected to a vacuum via a pressure control valve 4. It has a structure connected to an exhaust system 5, and 30 silicon wafers 6 are arranged in the reaction tube vertically to the tube axis direction. Here, 7 is a trap and 8 is a vacuum gauge.
ここで、まず、不純物拡散温度より低い炉内温
度1000℃に設定し、真空排気系を作動させること
により管内を減圧状態である3torrまで排気した
のち、ガス供給系からホスフイン（PH3）ガス20
c.c.／分窒素（N2）ガス１／分酸素（O2）ガス
200c.c.／分を流し、圧力コントロールバルブによ
つて管内の圧力が常に3torrとなるように制御し
つつ、シリコンウエハ表面上にリンの蒸着層を形
成する。次にPH3ガスを除去し、炉内温度を1100
℃に設定し20時間の熱処理を行いｎ型拡散領域を
形成する。 Here, first, the temperature inside the furnace is set to 1000℃, which is lower than the impurity diffusion temperature, and the inside of the tube is evacuated to a reduced pressure of 3 torr by operating the vacuum evacuation system, and then phosphine (PH 3 ) gas 20
cc/min Nitrogen (N 2 ) gas 1/min Oxygen (O 2 ) gas
A evaporated layer of phosphorus is formed on the surface of the silicon wafer by flowing 200 c.c./min and controlling the pressure inside the tube to always be 3 torr using a pressure control valve. Then remove the PH3 gas and reduce the furnace temperature to 1100
℃ for 20 hours to form an n-type diffusion region.
このようにして形成されたｎ型拡散領域につい
て層抵抗のばらつきを測定した結果を第２図ａ〜
ｄに実線で示す。点線は従来法を用いた場合の測
定結果で管内圧力を常圧とし、他の条件を同じく
した場合である。 The results of measuring the variation in layer resistance of the n-type diffusion region formed in this way are shown in Figure 2a-
d is shown by a solid line. The dotted line shows the measurement results using the conventional method, with the pipe internal pressure being normal pressure and other conditions being the same.
第２図ａおよび第２図ｂは、一枚のウエハ上で
のＸ、Ｙ方向に沿つた層抵抗のばらつきを示すも
ので、これらから明らかなように本発明の方法に
よると、一枚のウエハ内でのばらつきは±３％以
内と大きく改善されている。 Figures 2a and 2b show the variation in layer resistance along the X and Y directions on one wafer, and it is clear from these that according to the method of the present invention, one wafer The variation within the wafer has been greatly improved to within ±3%.
第２図ｃは、ウエハを配置する位置を横軸にと
り、層抵抗の規定平均値に対するばらつきを示し
たもので、この結果から明らかなように、本発明
の方法によるとウエハ間でのばらつきも±３％以
内と大きく改善されている。 Figure 2c shows the variation in layer resistance with respect to the specified average value, with the horizontal axis representing the position where the wafer is placed.As is clear from this result, the method of the present invention also reduces the variation between wafers. This is a significant improvement within ±3%.
第２図ｄは不純物拡散領域の形成を８ロツト繰
り返し、それぞれのロツト内での平均値を測定し
た結果を示す。横軸方向に第１回〜第８回をとつ
た。これからも明らかなように、ロツト間でのば
らつきも本発明の方法によると±３％以内と大き
く改善される。 FIG. 2d shows the results of repeating the formation of impurity diffusion regions in 8 lots and measuring the average value within each lot. The 1st to 8th times are plotted along the horizontal axis. As is clear from this, the method of the present invention greatly improves the variation between lots to within ±3%.
これらの測定結果からも明らかなように、本発
明の方法によるとウエハ内、ロツト中のウエハ
間、ロツト間での不純物拡散層の濃度および深さ
が常に均一化されたものとなる。従つて、低濃度
の場合も均一化が可能となり、本発明の方法によ
り1018〜1021cm-3の範囲で安定で均一な濃度の不
純物拡散層の形成が可能である。 As is clear from these measurement results, according to the method of the present invention, the concentration and depth of the impurity diffusion layer within a wafer, between wafers in a lot, and between lots are always made uniform. Therefore, even when the concentration is low, it is possible to make the impurity diffusion layer uniform, and the method of the present invention makes it possible to form an impurity diffusion layer with a stable and uniform concentration in the range of 10 18 to 10 21 cm −3 .
また反応管内で、不純物ガスが均一化されるた
めウエハ口径にも左右されることなく背中合せに
２枚一組としてウエハを配置してもよく、炉内の
均熱ゾーンの長さに応じて、一度に処理しうるウ
エハの枚数も大きく向上する。さらに本発明で
は、蒸着が減圧下でゆつくりなされるため、無理
な不純物押し込みがなされず、表面欠陥や歪の発
生が従来に比べて大きく軽減される。そして、管
内は減圧状態に保たれるため、反応管やボート、
ウエハの汚染が少なく歩留向上に寄与できる。従
つて、表面欠陥の少ないエミツタ拡散領域の形成
が容易となり、安定で良好な低雑音トランジスタ
の形成が可能となる。 In addition, since the impurity gas is homogenized in the reaction tube, the wafers can be placed back-to-back as a set without being affected by the wafer diameter, and depending on the length of the soaking zone in the furnace, The number of wafers that can be processed at one time is also greatly increased. Furthermore, in the present invention, since the vapor deposition is carried out slowly under reduced pressure, impurities are not forced into the structure, and the occurrence of surface defects and distortions is greatly reduced compared to the conventional method. Since the inside of the tube is kept under reduced pressure, the reaction tube, boat, etc.
There is less contamination of wafers, which can contribute to improved yield. Therefore, it becomes easy to form an emitter diffusion region with few surface defects, and it becomes possible to form a stable and good low-noise transistor.
以上説明してきたように、本発明の方法による
と、非常に作業性良く、安定で、均一な濃度の不
純物拡散領域の形成がなされ、半導体装置の拡散
工程に大きく寄与するものである。 As described above, according to the method of the present invention, an impurity diffusion region with very good workability, stability, and uniform concentration can be formed, which greatly contributes to the diffusion process of semiconductor devices.
第１図は本発明実施例の方法で用いる不純物蒸
着拡散装置の概略構成図、第２図ａ〜ｄは本発明
の実施例の方法を用いて形成した不純物拡散層の
層抵抗のばらつきの従来の方法を用いた場合との
比較図である。
１……炉、２……反応管、３……ガス供給系、
４……圧力コントロールバルブ、５……真空排気
系、６……半導体ウエハ、７……トラツプ、８…
…真空計。
FIG. 1 is a schematic configuration diagram of an impurity vapor deposition and diffusion apparatus used in the method of the embodiment of the present invention, and FIGS. It is a comparison diagram with the case using the method. 1...Furnace, 2...Reaction tube, 3...Gas supply system,
4... Pressure control valve, 5... Vacuum exhaust system, 6... Semiconductor wafer, 7... Trap, 8...
…Vacuum gauge.
Claims (1)
不純物を選択的に蒸着拡散するにあたり、不純物
拡散用マスクの形成された前記半導体基板が配置
されるとともに、不純物拡散温度よりも低い不純
物蒸着温度に保たれ、かつ、減圧状態とされた反
応管内へ不純物ガス、不活性ガスならびに酸化性
ガスの混合ガスを連続的に供給しながら前記半導
体基板上の全域に前記不純物を含む酸化膜を形成
したのち、前記混合ガス中の不純物ガスの供給の
みを断ち、次いで、前記反応管内の温度を不純物
拡散温度まで高め、前記酸化膜と直接接触する半
導体基板部分内へ前記酸化膜中の不純物を選択的
に拡散させることを特徴とする半導体装置の製造
方法。1. When selectively vapor depositing and diffusing an impurity of a desired conductivity type into a semiconductor substrate of one conductivity type, the semiconductor substrate on which an impurity diffusion mask is formed is placed, and the impurity vapor deposition temperature is lower than the impurity diffusion temperature. Forming an oxide film containing the impurity over the entire area on the semiconductor substrate while continuously supplying a mixed gas of an impurity gas, an inert gas, and an oxidizing gas into a reaction tube maintained at a temperature and under reduced pressure. After that, only the supply of the impurity gas in the mixed gas is cut off, and then the temperature inside the reaction tube is raised to the impurity diffusion temperature, and the impurities in the oxide film are selected into the portion of the semiconductor substrate that is in direct contact with the oxide film. 1. A method for manufacturing a semiconductor device, characterized by diffusing the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15956879A JPS5681927A (en) | 1979-12-07 | 1979-12-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15956879A JPS5681927A (en) | 1979-12-07 | 1979-12-07 | Manufacture of semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5094581A Division JPS56162830A (en) | 1981-04-03 | 1981-04-03 | Impurity depositing and diffusing device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5681927A JPS5681927A (en) | 1981-07-04 |
| JPH0120528B2 true JPH0120528B2 (en) | 1989-04-17 |
Family
ID=15696559
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15956879A Granted JPS5681927A (en) | 1979-12-07 | 1979-12-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5681927A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5068052A (en) * | 1973-10-17 | 1975-06-07 | ||
| JPS5468052A (en) * | 1977-11-08 | 1979-05-31 | Nippon Kankou Shikiso Kenkiyuu | Method of eliminating harmful used waste liquid of oxidant meter |
-
1979
- 1979-12-07 JP JP15956879A patent/JPS5681927A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5068052A (en) * | 1973-10-17 | 1975-06-07 | ||
| JPS5468052A (en) * | 1977-11-08 | 1979-05-31 | Nippon Kankou Shikiso Kenkiyuu | Method of eliminating harmful used waste liquid of oxidant meter |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5681927A (en) | 1981-07-04 |
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