JP2578914B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2578914B2 JP2578914B2 JP15327488A JP15327488A JP2578914B2 JP 2578914 B2 JP2578914 B2 JP 2578914B2 JP 15327488 A JP15327488 A JP 15327488A JP 15327488 A JP15327488 A JP 15327488A JP 2578914 B2 JP2578914 B2 JP 2578914B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- oxide film
- silicon substrate
- impurity
- tube
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Formation Of Insulating Films (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、半導体装置の製造方法、特に、シリコン基
板に不純物を拡散させる方法に関するものである。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for diffusing impurities into a silicon substrate.
従来の技術 従来、低圧蒸着装置を用いて不純物をシリコン基板上
に拡散する方法は、ｎ形の拡散層を形成する場合にはホ
スフィン（PH3）を、またｐ形の拡散層を形成する場合
にはジボランガス（B2H6）を酸素ガスと同時に、高温で
あらかじめ低圧にされたチューブ内に流し、チューブ内
に配置されたウェハのシリコン基板上に不純物を蒸着す
る。この後、拡散炉にウェハを挿入して不純物を拡散し
て拡散層、例えばエミッタ領域やベース領域を形成す
る。2. Description of the Related Art Conventionally, a method of diffusing impurities onto a silicon substrate using a low-pressure deposition apparatus is based on a method of forming phosphine (PH 3 ) when forming an n-type diffusion layer and forming a p-type diffusion layer. In this case, diborane gas (B 2 H 6 ) is flowed simultaneously with the oxygen gas into a tube which has been preliminarily reduced in pressure at a high temperature, and impurities are deposited on a silicon substrate of a wafer placed in the tube. After that, the wafer is inserted into a diffusion furnace to diffuse impurities to form a diffusion layer, for example, an emitter region and a base region.
発明が解決しようとする課題 従来の製造方法では、シリコン基板上に完全に酸化物
になったP2O5やB2O3が蒸着されるのみでなく、酸化され
ないリン（Ｐ）やボロン（Ｂ）が直接シリコンの基板上
に付着し、部分的に高濃度な層が形成される。この状態
で、拡散炉で不純物を拡散すると第２図ａに示すよう
に、シリコン基板１の上にトランジスタのエミッタ領域
２あるいはベース領域３の中に拡散層の一部が異常に速
く拡散された領域４が形成される。このことにより、第
２図ｂのＶ−Ｉ特性が示すようにトランジスタのコレク
タ・ベース耐圧（BVCBO）あるいはコレクタ・エミッタ
耐圧（BVCEO）等の耐圧が劣化し、歩留が低下する問題
があった。According to the conventional manufacturing method, not only is P 2 O 5 or B 2 O 3 completely turned into an oxide on a silicon substrate, but also phosphorus (P) or boron ( B) is deposited directly on the silicon substrate, forming a partially heavily doped layer. In this state, when the impurity was diffused in the diffusion furnace, a part of the diffusion layer was diffused abnormally rapidly into the emitter region 2 or the base region 3 of the transistor on the silicon substrate 1 as shown in FIG. 2A. Region 4 is formed. As a result, the withstand voltage such as the collector-base breakdown voltage (BV CBO ) or the collector-emitter breakdown voltage (BV CEO ) of the transistor deteriorates as shown by the VI characteristic in FIG. there were.
本発明はこのような耐圧劣化を防ぐ半導体装置を製造
することを目的とするものである。An object of the present invention is to manufacture a semiconductor device which prevents such deterioration in breakdown voltage.
課題を解決するための手段 本発明の半導体装置の製造方法は、減圧された炉内で
シリコン基板上に酸化シリコン膜を形成した後、続いて
前記炉に酸素ガスと不純物ガスとを導入して前記酸化膜
上に不純物を含有した酸化膜を形成し、熱拡散により前
記シリコン基板に前記不純物を拡散させて拡散層を形成
するものである。Means for Solving the Problems The method of manufacturing a semiconductor device according to the present invention comprises, after forming a silicon oxide film on a silicon substrate in a depressurized furnace, subsequently introducing an oxygen gas and an impurity gas into the furnace. An oxide film containing an impurity is formed on the oxide film, and the impurity is diffused into the silicon substrate by thermal diffusion to form a diffusion layer.
作用 本発明の半導体装置の製造方法によれば、不純物原子
（Ｐ又はＢ）が直接シリコン基板上に付着することがな
く、均一な不純物濃度の拡散層が形成され部分的な異常
拡散が防止できる。According to the method of manufacturing a semiconductor device of the present invention, a diffusion layer having a uniform impurity concentration is formed without directly attaching impurity atoms (P or B) on a silicon substrate, and partial abnormal diffusion can be prevented. .
実施例 本発明の半導体装置の製造方法の実施例を第１図に示
した低圧蒸着装置の概略図を参照して説明する。Embodiment An embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to the schematic view of the low-pressure deposition apparatus shown in FIG.
チューブ５の中に、あらかじめフォトリソグラフィを
用いて酸化膜の一部を除去して開口部を設けたシリコン
ウェハ６を挿入し、真空ポンプ７でチューブ５の中を減
圧にするとともに、ヒーター８でチューブ５の中のシリ
コンウェハ６を加熱する。次に酸素ボンベ９より酸素ガ
スをチューブ５内に流し込み、開口部のシリコンが露出
している部分に厚さが数100Åの酸化膜を形成する。続
いて酸素ボンベ９より酸素ガスと不純物ガスボンベ10よ
り不純物ガス（例えばPH3あるいはB2H6）を流して酸化
膜の上に不純物の混入した酸化膜を形成する。この後、
シリコンウェハ６をチューブ５から取り出し、シリコン
ウェハ６を拡散炉に入れ不純物を開口部より拡散して拡
散層を形成する。A silicon wafer 6 having an opening formed by removing a part of the oxide film by photolithography in advance is inserted into the tube 5, the inside of the tube 5 is reduced in pressure by a vacuum pump 7, and The silicon wafer 6 in the tube 5 is heated. Next, oxygen gas is flown into the tube 5 from the oxygen cylinder 9 to form an oxide film having a thickness of several hundreds of degrees at the portion where the silicon is exposed at the opening. Subsequently, an oxygen gas containing impurities is mixed on the oxide film by flowing an oxygen gas from the oxygen cylinder 9 and an impurity gas (for example, PH 3 or B 2 H 6 ) from the impurity gas cylinder 10. After this,
The silicon wafer 6 is taken out of the tube 5, and the silicon wafer 6 is placed in a diffusion furnace to diffuse impurities from the opening to form a diffusion layer.
このようにしてトランジスタのエミッタ領域とベース
領域を形成すると、直流電流増幅率（hFE）が均一でコ
レクタ−ベース間耐圧（BVCBO）やコレクタ−エミッタ
間耐圧（BVCEO）が大きな特性を得ることができる。When the emitter region and the base region of the transistor are formed in this way, the DC current gain (h FE ) is uniform, and the collector-base breakdown voltage (BV CBO ) and the collector-emitter breakdown voltage (BV CEO ) have large characteristics. be able to.
発明の効果 本発明の半導体装置の製造方法によれば、薄い酸化膜
の上に不純物を蒸着し、拡散するため、異常拡散が防止
でき、トランジスタの耐圧特性を向上させることができ
る。According to the method of manufacturing a semiconductor device of the present invention, impurities are deposited and diffused on a thin oxide film, so that abnormal diffusion can be prevented and the withstand voltage characteristics of the transistor can be improved.
第１図は本発明に用いる低圧蒸着装置の概略図、第２図
は従来の半導体装置の製造方法によるトランジスタの断
面図とそのＶ−Ｉ特性を示す図である。 ５……チューブ、６……シリコンウェハ、７……真空ポ
ンプ、８……ヒーター、９……酸素ボンベ、10……不純
物ガスボンベ。FIG. 1 is a schematic view of a low-pressure deposition apparatus used in the present invention, and FIG. 2 is a cross-sectional view of a transistor according to a conventional method of manufacturing a semiconductor device and a diagram showing its VI characteristics. 5 ... tube, 6 ... silicon wafer, 7 ... vacuum pump, 8 ... heater, 9 ... oxygen cylinder, 10 ... impurity gas cylinder.
Claims (1)
リコン膜を形成した後、続いて前記炉に酸素ガスと不純
物ガスとを導入して前記酸化膜上に不純物を含有した酸
化膜を形成し、熱拡散により前記シリコン基板に前記不
純物を拡散させて拡散層を形成する半導体装置の製造方
法。After a silicon oxide film is formed on a silicon substrate in a reduced-pressure furnace, an oxygen gas and an impurity gas are introduced into the furnace to form an oxide film containing impurities on the oxide film. Forming a diffusion layer by diffusing the impurity into the silicon substrate by thermal diffusion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15327488A JP2578914B2 (en) | 1988-06-21 | 1988-06-21 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15327488A JP2578914B2 (en) | 1988-06-21 | 1988-06-21 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01319933A JPH01319933A (en) | 1989-12-26 |
| JP2578914B2 true JP2578914B2 (en) | 1997-02-05 |
Family
ID=15558881
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15327488A Expired - Fee Related JP2578914B2 (en) | 1988-06-21 | 1988-06-21 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2578914B2 (en) |
-
1988
- 1988-06-21 JP JP15327488A patent/JP2578914B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01319933A (en) | 1989-12-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |