JPH04237118A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form the junction surface of a diffusion layer to be formed in a substrate into a uniform and stable surface. CONSTITUTION:A thin film 101, on which the tunnel phenomenon of carrier can be displayed, is formed on a substrate, a polycrystalline layer 10 is formed on the above-mentioned thin film 101, and the impurities, having the diffusion coefficient smaller than the aforesaid thin film, are implanted. The impurities implanted into the above-mentioned polycrystalline layer 10 are diffused in the polycrystalline layer 10 by conducting a first heat treatment, and a uniform impurity layer, or a practically uniform impurity layer, is formed on the grain boundary layer located between the polycrystalline layer 10 and the above- mentioned thin film 101. The impurities in the above-mentioned uniform, or practically uniform impurity layer are diffused into the substrate through the intermediary of the aforesaid thin film by conducting a second heat treatment, and a diffusion layer 3, which becomes each part of the device, is formed.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, a method for manufacturing a semiconductor device that includes a step of injecting impurities into a substrate through a polycrystalline layer to form diffusion layers that will become each part of the device. Regarding.

0002

2. Description of the Related Art FIG. 21 is a cross-sectional view of a Si substrate in which a diffusion layer is formed in order to explain a conventional method of manufacturing a semiconductor device. In the figure, 1 is a Si single crystal substrate (hereinafter referred to as a substrate), 102 and 103 are diffusion layers, and 10
10 is a polycrystalline Si deposited layer, and 10A is a crystal grain boundary (hereinafter referred to as grain boundary).

The diffusion layer 102 contains impurities as polycrystalline S.
It was formed by directly implanting it into the substrate 1 before forming the i deposited layer 1010, and the diffusion layer 103 was formed by implanting it through the polycrystalline Si deposited layer 1010.

That is, the diffusion layer 103 is formed by first implanting impurities into the polycrystalline Si deposited layer 1010 by ion implantation, and then by heat treatment, the impurities are removed from the polycrystalline Si deposited layer 1010 into the substrate 1.
It is formed by diffusion into the inside.

[0005]

However, as shown in the figure, in the diffusion layer 103 formed by such a conventional method, a deep junction 10D is formed in the junction region 10B between the substrate 1 and the grain boundary 10A, for example. be done. Therefore, the entire joint surface is not uniform. In the case of bipolar transistors in integrated circuits, this causes variations in collector current and current amplification factor.

Furthermore, in the conventional method, a natural oxide film (~5 Å) is formed between the polycrystalline Si and the substrate 1 in the step of depositing polycrystalline Si, but this oxide film is removed by heat treatment during impurity diffusion into the substrate 1. Partial destruction may occur. this is,
When the emitter junction is shallow, the effective diffusion distance of minority carriers injected into the emitter varies depending on the location within the emitter, causing variations in base current. In any of the above cases, the bonding surface becomes uneven, and this becomes a particularly important problem when the circuits formed on the substrate become highly integrated and the thickness of the emitter layer and base layer becomes thinner. It's coming.

The present invention has been made to solve the above problems, and its purpose is to provide a method for manufacturing a semiconductor device in which the diffusion layers forming each part of the device can have a uniform bonding surface. .

[0008]

[Means for Solving the Problems] In order to achieve the above object, the method for manufacturing a semiconductor device of the present invention includes forming a thin film on a substrate in which carrier tunneling is possible, and forming a polycrystalline layer on the thin film. forming the polycrystalline layer, implanting an impurity whose diffusion coefficient is smaller in the thin film from the surface of the polycrystalline layer, and diffusing the impurity implanted into the polycrystalline layer into the polycrystalline layer by a first heat treatment, A uniform or substantially uniform impurity layer is formed in a grain boundary layer between the polycrystalline layer and the thin film, and impurities in the uniform or substantially uniform impurity layer are removed by a second heat treatment to form the thin film. It diffuses into the substrate through the substrate, forming a diffusion layer that becomes each part of the device.

[0009]

[Operation] The present invention diffuses the impurities injected from the surface of the polycrystalline layer into the polycrystalline layer by the first heat treatment, so that the impurities are uniformly or substantially uniformly distributed in the grain boundary layer between the polycrystalline layer and the thin film. Form an impurity layer. Thereafter, a second heat treatment diffuses the impurities in the uniform or substantially uniform impurity layer into the substrate through the thin film, forming a diffusion layer having a uniform bonding surface that becomes each part of the device.

0010

Embodiments Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings.

FIGS. 1 to 6 are diagrams showing the main manufacturing steps for a silicon-npn bipolar transistor according to an embodiment of the present invention.

FIGS. 7, 8, and 9 are graphs showing temperature conditions during the first heat treatment and the second heat treatment.

The method of forming each part will be explained in order according to FIGS. 1 to 6.

(a) First, as shown in FIG. 1, a p-type diffusion layer 2 and an oxide film 100, which will become the base of a transistor, are formed on an n-type substrate 1.

Next, as shown in FIG. 2, after forming a contact hole for forming an emitter by etching, an ultra-thin oxide film 101 having an impurity diffusion coefficient smaller than that of polycrystalline Si is formed.
(with a thickness of 500 Å or less) (hereinafter referred to as "tunnel oxide film").

(b) Next, as shown in FIG. 3, polycrystalline Si is deposited by low pressure chemical vapor deposition (LPCVD) to form a polycrystalline Si deposited layer 10. Impurity species such as As and P are implanted into the substrate 1 from the surface of the deposited layer 10 by ion implantation to form a region 11 indicated by a broken line.

(c) Next, as shown in FIG. 4, impurities are diffused into the region of the polycrystalline Si deposited layer 10 up to at least this side of the tunnel oxide film 101 through a first heat treatment (at a constant temperature of 600 to 800° C.). Then, a uniform impurity layer is formed in the grain boundary layer between the tunnel oxide film 101 and the grain boundary layer.

(d) Next, as shown in FIG. 5, impurities are removed from the impurity layer formed by the first heat treatment shown in FIG.
At a constant temperature of 0° C.), the tunnel oxide film 101 is passed through to form an n+ diffusion layer 3 which will become an emitter. Here, the temperature increase between the first heat treatment and the second heat treatment is a fairly rapid temperature increase (5° C./min.) as shown in FIG.

(e) Next, as shown in FIG. 6, the polycrystalline Si deposited layer 10 is patterned to form electrodes.

[0020] The above production process includes step (d) and step (e).
It is also possible to carry out the temperature increase sequentially without dividing the temperature by a gradual continuous temperature increase as shown in FIG. 8, or by a stepwise temperature increase as shown in FIG. In this case, the first heat treatment is performed on the low temperature side of the figure, and the second heat treatment is performed on the high temperature side of the figure.

[0021] The above two types of steps make it possible to simplify the process. In addition, step (e) is a rapid heat treatment (R
TA) method, high temperature (e.g. 1000°C), short time (
For example, heat treatment for 10 seconds) may be used instead.

Next, we will discuss diffusion in polycrystals.

A polycrystal is a collection of single crystals with a size distribution, and the crystal grains do not have a fixed crystal orientation. Each of the crystal grains has a grain boundary, which is a grain boundary, and there is significant lattice disorder. The existence of these grain boundaries is the reason why polycrystals have different characteristics from single crystals.

The diffusion of impurities is also greatly affected by the grain size of each crystal grain and the lattice defect density at grain boundaries.

That is, diffusion in polycrystals can be roughly divided into diffusion through grain boundaries (diffusion constant Dgb) and diffusion within each grain (diffusion constant Dg), and the overall effective diffusion constant Deff is expressed by the following formula.

Deff=(1-f)Dg+fDgb...
- (1) Here, f is the rate at which impurity species exist at grain boundaries. In terms of the model, when the cubic grain size is used, f=3k・delta/Lg ・・・・・・・・・・・・
...(2). However, k: segregation coefficient to grain boundaries, de
lta: Grain boundary width, Lg: Crystal grain size.

[0027] Here, the value of k is usually 1 or more, and 20
The value is said to be approximately 1250. Also, delta is ~5 Å, Lg is determined by the polycrystalline deposition conditions, and is 1
00 Å to several thousand Å. In the case of polycrystals, usually Dgb≫D
It is g. Also, the relationship between Deff and D is Deff
≫D.

FIG. 10 is a graph showing the diffusion coefficient for n-type impurities. In the figure, the horizontal axis is 1000/T
(°K), and the vertical axis is the diffusion coefficient (Equation 1) (μm/
hr1/2).

In the figure, the diffusion coefficient in a single crystal (Equation 1
), impurities As, Bi, and P are shown, and the effective diffusion coefficient in polycrystals (Equation 2) (indicated by × mark) and the grain boundary diffusion coefficient (Equation 3) (indicated by △ mark) are shown. The figure shows only the impurity As. As you can see from the figure, A
The diffusion coefficient of s in a single crystal (Equation 1), the effective diffusion coefficient in a polycrystal (Equation 2), and the grain boundary diffusion coefficient (Equation 3) are each 1.
It differs by about 0 times. FIG. 11 is a graph showing the diffusion coefficient for p-type impurities.

In the figure, the diffusion coefficient in a single crystal (Equation 1
) are shown for impurities Al, B, Ga, In, and Tl, and the effective diffusion coefficient in polycrystal (Equation 2) (indicated by × mark) and the grain boundary diffusion coefficient (Equation 3) (indicated by △ mark) The following is shown for impurity B. As can be seen from the figure, impurity B
It is clear that each diffusion coefficient differs by about one digit in the order of (Equation 4).

The above-mentioned segregation coefficient k is the ratio of the ratio of impurities occupying sites in grain boundaries to the ratio of impurities occupying sites in crystal grains, and depends on the type, concentration, temperature, grain size, etc. of impurities. Qualitatively, it is small at high concentrations and high temperatures. Also, As, P, etc. are large,
B is small. An example is shown in FIG. 12 (however, there are differences depending on the literature).

FIG. 13 is a graph showing the diffusion coefficient of impurities in a SiO2 single crystal, and shows an example where the constant rate of diffusion is slow. In the figure, the horizontal axis is 1
000/T (°K-1), and the vertical axis is (Equation 1) (μ/
hr1/2). Impurities are shown for As and P.

From the figure, the diffusion coefficient of As in SiO2 is two orders of magnitude (~1/1) higher than the grain boundary diffusion coefficient shown in FIG.
00).

Next, the reason why the diffusion layer is uniformly formed in the substrate according to the present invention will be explained. Tunnel oxide film 1
When a polycrystalline Si layer 10 is deposited on top of SiO2, grain boundaries inevitably occur between SiO2 and polycrystalline Si.

FIG. 14 shows the polycrystalline Si shown in FIGS. 1 to 6.
1 is an enlarged view of a deposited layer 10, a tunnel oxide film 101, and a single crystal Si substrate 1. FIG.

In the figure, the impurity ion-implanted into the polycrystalline Si deposited layer 10 has a grain boundary diffusion coefficient (Equation 3) that is more than 10 times larger than the diffusion coefficient in the crystal grains (Equation 5). Therefore, most of it diffuses along the grain boundary 7A (indicated by arrow V). Furthermore, since the segregation coefficient is large at the grain boundary 7A, a high concentration region is formed along this grain boundary 7A. Since there is also a grain boundary between the tunnel oxide film 101 and the polycrystalline Si deposited layer 10, impurities quickly diffuse into this grain boundary 7C (indicated by arrow H). For example, in the locations indicated by 7B1 and 7B2 in the figure, abnormal diffusion into the single crystal of the substrate 1 is prevented because the tunnel oxide film 101 serves as a diffusion barrier. Then, a uniform high concentration impurity layer is formed at the grain boundary 7C. Then, by the next second heat treatment, a tunnel oxide film 10 is formed from this grain boundary layer 7C into the substrate 1.
Impurities are diffused through the substrate 1, and a uniform diffusion layer (layer indicated by 3 in FIGS. 5 and 6) is formed in the substrate 1. By passing through the tunnel oxide film 101 in this manner, impurities are uniformly diffused from the polycrystalline Si deposited layer 10 into the substrate 1, forming a uniform diffusion layer. However, in the absence of this tunnel oxide film 101, abnormal diffusion occurs in 7B1 and 7B2, and the junction surface is formed non-uniformly.

[0037]

[Math 1]

[0038]

[Math 2]

[0039]

[Math 3]

[0040]

[Math 4]

[0041]

[Equation 5] Furthermore, when diffusing impurities through a natural oxide film,
When performing the second heat treatment, polycrystalline Si is usually heated at 950°C or higher.
Recrystallization occurs, and this is particularly noticeable at the interface between polycrystalline Si and the single crystal, where lattice rearrangement occurs epitaxially from the single crystal region 1, resulting in variations in the shape of the junction, and the junction surface becomes uneven. It becomes uniform. This causes variations in the current amplification factor hFE in the case of bipolar transistors in integrated circuits. In order to prevent the above phenomena,
There is a particular need to create a thin, stable oxide film.

FIG. 15 is a graph showing the relationship between the thickness of an oxide film and time when an oxide film is formed by implanting oxygen by rapid thermal heating (RTA). In the figure, the horizontal axis is time (seconds) and the vertical axis is film thickness (Å). The parameter is temperature (°C).

As is clear from the figure, the reproducibility of the film formation is good when the film thickness is 10 Å or more, and therefore it can be seen that the film can be formed stably.

Materials that can be used as a diffusion barrier as described above include not only SiO2 but also SiO2.
Similarly, S has a lower impurity diffusion rate than polycrystalline Si.
There are i3 N4, SiC, etc. However, in this case as well, the film thickness usually needs to be about 50 Å or less so that carriers can easily pass through due to the tunnel effect. Note that since the natural oxide film is not stably formed, it has many pinholes and is weak and damaged by the second heat treatment, so it is impossible to utilize this film. On the contrary, it increases the variation in bipolar transistors and the like. Therefore, in order to eliminate the influence of this natural oxide film, it is necessary to introduce an ultra-thin film forming process as in the present invention.

FIGS. 16 to 20 are diagrams showing the manufacturing process of a silicon-npn bipolar transistor according to another embodiment of the present invention.

The difference from the method shown in FIGS. 1 to 6 of this embodiment is the step shown in FIG. 19 in which the base region 2 is also formed by diffusion through an oxide film, and then in the step shown in FIG. The point is that the region 3 which becomes the emitter is formed through the tunnel oxide film 101, and the base and emitter layers are formed by double diffusion.

This method also allows the base and emitter layers to be formed in a self-aligned manner. By diffusing impurities through the tunnel oxide film in this way, various diffusion layers can be formed.

Although the formation of the base extraction portion is not described in FIG. 20, after this, B is ion-implanted using the electrode 10 as a mask to form the external base region 20, thereby forming it in a self-aligned manner. You can also.

Alternatively, the electrodes can be taken out by first creating this external base region 20 around the base.

As explained above, by forming a thin film such as the tunnel oxide film in this example on a substrate, abnormal diffusion of impurities and polycrystalline recrystallization can be prevented.
A diffusion layer having a uniform bonding surface can be formed.

Therefore, in the case of a bipolar transistor formed on a substrate, its characteristics can be made uniform, base current leakage can be prevented, and the current amplification factor can be increased.

Furthermore, when the present invention is applied to an optical sensor, variations in its characteristics can be reduced, and S/N
It is possible to create a high-performance photoelectric conversion device with a large ratio.

[0053]

As explained above, according to the present invention, since impurities are implanted from the polycrystalline layer into the substrate through the thin film, recrystallization and natural oxidation of polycrystals by heat treatment as in the conventional method can be avoided. Damage to the film and damage to the bonding surface due to ion implantation can be prevented, and the bonding surface of the diffusion layer formed in the substrate can be made into a uniform and stable bonding surface. Therefore, it is possible to form a very thin diffusion layer suitable for high integration.

In the case of bipolar transistors formed on a substrate, there is no variation in characteristics, and a high-performance integrated circuit can be created.

Similarly, in the case of a photosensor formed on a substrate, an improvement in the S/N ratio can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a manufacturing process of a silicon-npn bipolar transistor according to an embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of a silicon-npn bipolar transistor, which is an embodiment of the present invention.

FIG. 3 is a diagram showing a manufacturing process of a silicon-npn bipolar transistor according to an embodiment of the present invention.

FIG. 4 is a diagram showing a manufacturing process of a silicon-npn bipolar transistor according to an embodiment of the present invention.

FIG. 5 is a diagram showing a manufacturing process of a silicon-npn bipolar transistor according to an embodiment of the present invention.

FIG. 6 is a diagram showing a manufacturing process of a silicon-npn bipolar transistor according to an embodiment of the present invention.

FIG. 7 is a graph showing temperature conditions during first heat treatment and second heat treatment.

FIG. 8 is a graph showing temperature conditions during first heat treatment and second heat treatment.

FIG. 9 is a graph showing temperature conditions during first heat treatment and second heat treatment.

FIG. 10 is a graph showing the diffusion coefficient of n-type impurities in Si crystal.

FIG. 11 is a graph showing the diffusion coefficient of p-type impurities in Si crystal.

FIG. 12 is a table of segregation coefficients at polycrystalline Si grain boundaries.

FIG. 13 is a graph showing the diffusion coefficients of impurities As and P in SiO2 crystal.

FIG. 14 is the polycrystalline Si deposited layer 10 shown in FIG. 1. 1 is an enlarged cross-sectional view of a tunnel oxide film 101 and a single crystal Si substrate 1. FIG.

FIG. 15 is a graph showing the relationship between the thickness of an oxide film and the implantation time when an oxide film is formed by implanting O2 using the rapid heating (PTA) method.

FIG. 16: Silicon-npn, another embodiment of the present invention.
It is a figure which shows the manufacturing process of a bipolar transistor.

FIG. 17: Silicon-npn, another embodiment of the present invention.
It is a figure which shows the manufacturing process of a bipolar transistor.

FIG. 18: Silicon-npn, another embodiment of the present invention.
It is a figure which shows the manufacturing process of a bipolar transistor.

FIG. 19: Silicon-npn, another embodiment of the present invention.
It is a figure which shows the manufacturing process of a bipolar transistor.

FIG. 20: Silicon-npn, another embodiment of the present invention.
It is a figure which shows the manufacturing process of a bipolar transistor.

FIG. 21 is a cross-sectional view of a Si substrate when a diffusion layer is formed in the Si substrate for explaining a conventional method.

[Explanation of symbols]

1 Si single crystal substrate, 2 diffusion layer, 3
Diffusion layer, 10 Polycrystalline Si deposited layer, 101
tunnel oxide film, 102 diffusion layer, 103
Diffusion layer, 7A grain boundary, 7B grain boundary, 7C grain boundary, 10A grain boundary,
10B grain boundary.

Claims (4)

[Claims] 1. A thin film capable of carrier tunneling is formed on a substrate, a polycrystalline layer is formed on the thin film, and the thin film has a smaller diffusion coefficient from the surface of the polycrystalline layer. A certain impurity is implanted into the polycrystalline layer, and the impurity implanted into the polycrystalline layer is diffused into the polycrystalline layer by a first heat treatment, so that the grain boundary layer between the polycrystalline layer and the thin film is uniformly or substantially A uniform impurity layer is formed, and impurities in the uniform or substantially uniform impurity layer are diffused into the substrate through the thin film by a second heat treatment to form a diffusion layer that becomes each part of the device. A method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first heat treatment and the second heat treatment are performed successively by successive temperature increases. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the first heat treatment and the second heat treatment are performed successively by increasing the temperature in stages. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the material of the substrate is a semiconductor material containing Si.