JPH02256248A - Manufacture of thin film semiconductor element - Google Patents

Abstract

PURPOSE:To form a drain self-aligned with a gate without using ion implantation by a method wherein diffusion is performed by using an impurities diffusion source deposited on an entire surface without patterning. CONSTITUTION:An SiO2 layer 3 deposited by thermal oxidation or CVD is formed on the surface of a first type semiconductor thin film 2. Then n-type poly-Si for example is deposited as a gate electrode 4 and patterned. Then with the gate electrode 4 as a mask, reactive ion etching is performed to open a diffusion window of a source drain so that a semiconductor diffusion source 5 of a second conductive type semiconductor region doped with impurities is formed on an entire surface. Then second conductive type impurities are diffused in an oxidizing atmosphere to form a source 6 and a drain 7 regions. Thus a source drain can be formed self-aligned with a gate without using ion implantation.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device formed on an insulating substrate, and in particular, to the manufacture of a semiconductor device in which impurity diffusion can be performed in a self-aligned manner. Regarding the method.

[Prior art and its problems] A method of diffusing impurities into a semiconductor layer involves using polycrystalline silicon doped with a high concentration of impurities.
-5i: DOPOS) is used as a diffusion source. As shown in FIG. 2, in this method, a gate insulating film is formed on the surface of a semiconductor thin film 401, and the gate insulating film 401 is
2 (this film also serves as a diffusion mask) and the diffusion window 40.
In this method, after opening a hole 3, DOPO 5 is deposited on the entire surface, a gate electrode 1404 and a source/drain diffusion source 405 are formed by patterning, and then impurities are diffused into the semiconductor layer through a diffusion window 403. However, this method requires a sufficient alignment margin between the diffusion window 403 and the gate electrode 404, and the gate length is also
4 and the patterning accuracy of the source/drain diffusion sources 405, it is difficult to form them finely and the formation speed is poor.

Further, when forming a semiconductor element on an insulating substrate, there is a method of diffusing impurities by ion implantation (FIG. 3). In this method, for example, the gate electrode 302
In this method, ions are implanted into the entire surface of the semiconductor N301 using the impurity diffusion region 303 as a gate electrode 3.
02 and self-line.

However, with this method, the ion implantation equipment is expensive,
Furthermore, using a substrate of any shape other than a wafer requires improvements to the susceptor, etc., making the device even more expensive.

As described above, conventionally, there has been no method for forming gates, sources, and drains by self-alignment with high precision and low cost by diffusion of impurities.

According to the present invention, by performing diffusion using an impurity diffusion source deposited over the entire surface without patterning, sources and drains can be formed in the gate and self-alignment line without using ion implantation.

Further, according to the present invention, source/drain diffusion windows can be formed in the gate electrode and the self-alignment line without performing resist patterning.

[Means for Solving the Problems] The gist of the present invention is to manufacture a semiconductor element in which a semiconductor region of a second conductivity type is formed in a predetermined region of a semiconductor layer of a first conductivity type formed on an insulating substrate. The method includes forming an insulating layer on the surface of a semiconductor layer of a first conductivity type, forming a gate electrode on the insulating layer, and performing reactive ion etching using the gate electrode as a mask to form a source and a drain. a step of opening a diffusion window; a step of forming a semiconductor diffusion source doped with an impurity which is a semiconductor region of the second conductivity type on the entire surface; Diffusion into a semiconductor layer of a conductivity type to form a source/drain region.

[Function] Since the present invention has the above configuration, the source/drain can be formed in the gate and self-alignment line without using ion implantation by performing diffusion using an impurity diffusion source deposited on the entire surface without buttering. can be formed.

Further, according to the present invention, source/drain diffusion windows can be formed in the date electrode and self-alignment line without performing resist patterning.

(Example of implementation) Embodiments of the present invention will be described in detail below with reference to the drawings.

A semiconductor thin film 2 of a first conductivity type is formed on an insulating substrate 1 . As the semiconductor thin film 2, a single crystal or polycrystalline St film is used. As the single crystal silicon, polycrystalline silicon recrystallized by laser annealing, minute Si on 5in2, and flattened single crystal grown by a single crystal growth method with an N4 pattern of 5eed can be used. can.

As polycrystalline St, LP- using ordinary silane gas is used.
Paily-3t with grain size ~500 deposited by CVD, a-3t deposited by LP-CVD or bladder vcVD, which is polycrystalized by heat treatment, and the above-mentioned POJ! 3/-
It is possible to use a polycrystalline layer obtained by ion-implanting St" into St and heat-treating it, or a polysilicon layer with a large grain size using the selective deposition method disclosed by the present applicant in JP-A-62-81711. .

Formation of such a polysilicon layer having a large grain size may be performed, for example, as follows.

A continuous film of Si and N is formed on a substrate, and by patterning, nucleation surfaces 3 of several tens of μm to several hundred μm square are formed separated from each other. As this nucleation surface, for example, CVD
Lithography of a silicon nitride layer (e.g. Si3N4 layer) or Si” implanted 5i02 by React
It may be formed by ive ton etching or ion implantation.

For example, the Si3N4 layer is SiH2Cl12 +NH
Using 3 gases, 0.3 Torr, heating temperature 800℃
It is sufficient to deposit it to a thickness of 0.1 μm under the following conditions.

For example, to implant St" ions into the surface of the 5i02 substrate, cover the surface of the 5i02 substrate with a resist, pattern a window, and implant Si+ on the entire surface at 20 keV and 1xlO1.
Ion implantation may be performed with a doping amount of 6 cm-' or more. Of course, a focused ion beam may be used without using a mask resist.

Subsequently, St polycrystals are selectively grown from the nucleation surface, and since the grain size of the polycrystalline grains can be controlled by temperature, it may be controlled by temperature.

Note that the particle size can also be controlled by adding a nucleation density control gas (for example, HCλ gas) together with the source gas. That is, in order to have complete selectivity, it is desirable to set the amount of HCfL to 1.0 (j2/m1n) or more.

Now, a Si02 layer 3 deposited by thermal oxidation or CVD on the surface of the first type semiconductor thin film 2 provided in this manner.
form. Next, as the gate electrode 4, for example, an n-type poI
Deposit and pattern Ly-3i (FIG. 1B).

Next, anisotropic etching is performed using reactive ion etching. At this time, etching is performed leaving the gate and the SiO2 on the side surfaces of the semiconductor thin film 2, and only the SiO2 on the top surface of the semiconductor thin film can be removed (FIG. 1C). At this time, the Si under the gate electrode is not removed, and this SiO2 becomes a gate insulating film.

Next, a polycrystalline Si layer or amorphous St layer 5 containing a high concentration of impurities of the second conductivity type is deposited on the entire surface (
Figure 1 D). The polycrystalline Si layer can be formed by ordinary LP-CVD. Further, as the amorphous Si, one made by LP-CVD or PuasmaCVD can be used.

Next, the impurity of the second conductivity type is diffused in an oxidizing atmosphere to form the source 6 and drain 7 regions, and the polycrystalline St or amorphous Si is entirely oxidized to form the oxide layer 8 (first Figure E). When diffusing to the source 6/drain 7 region, the gate electrode, the gate insulating film, and the 5in2 side surface of the semiconductor thin film 2 serve as a diffusion mask, and as a result, the gate, source, and drain can be formed in a self-aligned line.

Furthermore, by oxidizing all the impurity diffusion sources, the source/drain electrodes and the gate electrode can be electrically insulated.

[Example] Hereinafter, an example of the present invention will be described in detail using the drawings.

On the quartz substrate 1, St,
A film of 1000 N was deposited over the entire surface.

The deposition conditions were parallel plate pflasma-CVD.
Using the device, SiH4 (10% H2 dilution) flow rate t5se
cm, NH310sccrrt, pressure 0.16Torr
, under the conditions of discharge output 3.5W and substrate temperature 400℃, 20
Deposition was carried out for minutes.

Next, normal photolithographic patterning is performed, and later S
A region was formed in which f was selectively deposited. This selectively deposited Sf layer will later become a device formation region.

Next, polycrystalline Si2 was deposited on the above-described patterning region by CVD. The deposition conditions include SiC4!4 as a source gas and HCl2 as an etching gas.
．． H2 as carrier gas, 82 as doping gas
The test was carried out using H8 under conditions of a pressure of 150 TorrS and a temperature of 1000°C. Under these conditions, the particle size is approximately 1 μm1 and the impurity concentration is fEf5cm only on the above patterning region.
-' polycrystalline St was deposited.

Next, a 500-Si film was formed on the polycrystalline Si2 by a conventional thermal oxidation method.

Next, by low pressure CVD method, n
4000 types of poJly-3i were deposited and patterned to form gate electrodes.

Next, reactive ion etching, which is a well-known technique, was performed using a CF 4 /H 2 gas system and using the gate electrode as a mask. This etching removed only the oxide film on the source/drain diffusion regions.

Next, 2000 layers of n-type poly-3i5 were deposited by the reduced pressure CV method. As for the deposition conditions, SiH41
50sec, PH, (0.5% N2 dilution) 15sec
m, pressure 0.2 Torr.

Deposition was carried out at a temperature of 600° C. for 55 minutes.

Next, heat treatment was performed in an O2 atmosphere using a heat diffusion furnace. During this heat treatment, from the n-type pofLy-3iS,
At the same time that P diffused into polycrystalline Si2 to form source/drain regions, all of the n-type pony-3i5 could be oxidized.

Moreover, even with this heat treatment, P
had not spread at all.

Therefore, the gate, source, and drain can be formed in the self-line by this heat treatment, and since all of the n-type poIly-Si5, which is the impurity diffusion source, has been oxidized, electrical insulation between the source and drain electrodes and the gate electrode is also achieved. There was no problem.

When gate, source, and drain electrodes were formed on the MOSFET thus formed, the gate length was 2.
On-off operation of MOSFETs down to μm was confirmed.

[Effects of the Invention] As described above, according to the present invention, sources and drains can be formed on gates and self-aligned lines without using ion implantation.

Further, by oxidizing all the impurity diffusion sources at the same time as the impurity diffusion, the source/drain electrodes and the gate electrode can be electrically insulated.

[Brief explanation of drawings]

Figures 1A-E are process sectional views showing an embodiment of the present invention;
FIG. 3 and FIG. 3 are diagrams showing a conventional example. 1... Substrate, 2... Semiconductor thin film, 3... Insulating film,
4... Gate electrode, 5... Impurity diffusion source, 6...
Source electrode, 7... Each drain electrode, 8... Oxide film. Figure (A) (C) (D) (E)

Claims (2)

[Claims] (1) In a method for manufacturing a semiconductor device in which a semiconductor region of a second conductivity type is formed in a predetermined region of a semiconductor layer of a first conductivity type formed on an insulating substrate, the semiconductor layer of the first conductivity type is a step of forming an insulating layer on the surface; a step of forming a gate electrode on the insulating layer; a step of performing reactive ion etching using the gate electrode as a mask to open source/drain diffusion windows; forming a semiconductor diffusion source doped with impurities, which is a semiconductor region of a conductivity type, over the entire surface; diffusing impurities in the semiconductor diffusion source of the second conductivity type into the semiconductor layer of the first conductivity type; - A method for manufacturing a semiconductor device, comprising the step of forming a drain region. (2) Impurities in the semiconductor diffusion source of the second conductivity type are removed from the first conductivity type.
2. The method of manufacturing a semiconductor device according to claim 1, wherein said diffusion source of said second conductivity type is oxidized at the same time as said second conductivity type semiconductor layer is diffused into said second conductivity type semiconductor layer to form source/drain regions.