JPS5680735A - Line monitor control system - Google Patents

Line monitor control system

Info

Publication number
JPS5680735A
JPS5680735A JP15864079A JP15864079A JPS5680735A JP S5680735 A JPS5680735 A JP S5680735A JP 15864079 A JP15864079 A JP 15864079A JP 15864079 A JP15864079 A JP 15864079A JP S5680735 A JPS5680735 A JP S5680735A
Authority
JP
Japan
Prior art keywords
line
adapters
terminal device
control system
adapter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15864079A
Other languages
Japanese (ja)
Inventor
Noboru Yamamoto
Kenichi Okada
Shinji Sasaki
Ikumichi Unami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15864079A priority Critical patent/JPS5680735A/en
Publication of JPS5680735A publication Critical patent/JPS5680735A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to monitor even a high-speed circuit by branching a line at the terminal device side of a line adapter to another line adapter and by making it possible to use line adapters as they are for monitoring.
CONSTITUTION: As for line adapters 6-0 and 6-3 connected to terminal devices 7, reception line 10R and transmission line 10S at terminal device sides are branched and connected to other line adapters 6-1, 6-2, 6-4, and 6-5. When data transmission and reception are performed between data buffer area 15-0 and terminal device 7-0 via line adapter 6-0, those data are branched to and received by line adapters 6-1 and 6-2 and written in data buffer areas 15-1 and 15-2. Further, processor 1 is interrupted to dump the contents of buffer areas 15-1 and 15-2 to memory devices 8 and 9.
COPYRIGHT: (C)1981,JPO&Japio
JP15864079A 1979-12-06 1979-12-06 Line monitor control system Pending JPS5680735A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15864079A JPS5680735A (en) 1979-12-06 1979-12-06 Line monitor control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15864079A JPS5680735A (en) 1979-12-06 1979-12-06 Line monitor control system

Publications (1)

Publication Number Publication Date
JPS5680735A true JPS5680735A (en) 1981-07-02

Family

ID=15676121

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15864079A Pending JPS5680735A (en) 1979-12-06 1979-12-06 Line monitor control system

Country Status (1)

Country Link
JP (1) JPS5680735A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5387615A (en) * 1977-01-12 1978-08-02 Hitachi Ltd Line trouble detection system
JPS5432938A (en) * 1977-08-19 1979-03-10 Nippon Telegr & Teleph Corp <Ntt> Test monitor system of on-line data communication system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5387615A (en) * 1977-01-12 1978-08-02 Hitachi Ltd Line trouble detection system
JPS5432938A (en) * 1977-08-19 1979-03-10 Nippon Telegr & Teleph Corp <Ntt> Test monitor system of on-line data communication system

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