JPS55121537A - Function test processing system of communication controller - Google Patents

Function test processing system of communication controller

Info

Publication number
JPS55121537A
JPS55121537A JP2894879A JP2894879A JPS55121537A JP S55121537 A JPS55121537 A JP S55121537A JP 2894879 A JP2894879 A JP 2894879A JP 2894879 A JP2894879 A JP 2894879A JP S55121537 A JPS55121537 A JP S55121537A
Authority
JP
Japan
Prior art keywords
data
memory
communication controller
received data
data area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2894879A
Other languages
Japanese (ja)
Inventor
Shinji Ineshima
Masanobu Sato
Kunio Sato
Masao Gohara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2894879A priority Critical patent/JPS55121537A/en
Publication of JPS55121537A publication Critical patent/JPS55121537A/en
Pending legal-status Critical Current

Links

Landscapes

  • Computer And Data Communications (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)

Abstract

PURPOSE: To simplify a fault check by making it easy to demarcate a fault region by enabling the warpping of a memory part, and then by varying the timing of data transfer between this main part and a host data processor at need.
CONSTITUTION: This communication controller consists of interface part 5, main control part 6, circuit control part 8, circuit connection part 9, and memory part 7. Then, wrap data transfer method 15 is provided which sets the content of transmitted data area 10S concerned with transmitted data in memory part 7 in received data area 10R concerned with received data in the memory part and on the basis of memory wrap indication commands from host data processors 1 and 2, transmitted data is set in transmitted data area 10S, set in received data area 10 via transfer method 15, and then transferred as received data to the host data processor side.
COPYRIGHT: (C)1980,JPO&Japio
JP2894879A 1979-03-13 1979-03-13 Function test processing system of communication controller Pending JPS55121537A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2894879A JPS55121537A (en) 1979-03-13 1979-03-13 Function test processing system of communication controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2894879A JPS55121537A (en) 1979-03-13 1979-03-13 Function test processing system of communication controller

Publications (1)

Publication Number Publication Date
JPS55121537A true JPS55121537A (en) 1980-09-18

Family

ID=12262622

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2894879A Pending JPS55121537A (en) 1979-03-13 1979-03-13 Function test processing system of communication controller

Country Status (1)

Country Link
JP (1) JPS55121537A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02154548A (en) * 1988-12-07 1990-06-13 Hitachi Ltd Test method for on-line system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02154548A (en) * 1988-12-07 1990-06-13 Hitachi Ltd Test method for on-line system

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