JPS5682938A - Data buffer control system - Google Patents

Data buffer control system

Info

Publication number
JPS5682938A
JPS5682938A JP15953079A JP15953079A JPS5682938A JP S5682938 A JPS5682938 A JP S5682938A JP 15953079 A JP15953079 A JP 15953079A JP 15953079 A JP15953079 A JP 15953079A JP S5682938 A JPS5682938 A JP S5682938A
Authority
JP
Japan
Prior art keywords
data
data buffer
buffer area
channel device
transmitted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15953079A
Other languages
Japanese (ja)
Other versions
JPS6027427B2 (en
Inventor
Noboru Yamamoto
Kenichi Okada
Shinji Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP54159530A priority Critical patent/JPS6027427B2/en
Publication of JPS5682938A publication Critical patent/JPS5682938A/en
Publication of JPS6027427B2 publication Critical patent/JPS6027427B2/en
Expired legal-status Critical Current

Links

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  • Bus Control (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE: To improve the efficiency of utilization of a data buffer area in a data processing system having plural input-output adapters, by providing on a channel device a copy memory area wherein the contents of the data buffer area are copied.
CONSTITUTION: When central processor 1 transmits data to a terminal device via circuit control adapter 6-0, central processor 1 sets transmitted data 8 in data buffer area 7 in main memory device 2 and sends a send command to channel device 4. In response to the command, channel device 4 loads all transmitted data 8 or data buffer area 7 into copy memory area 11 and releases data buffer area 7. Data buffer area 7 can, therefore, be used for the storage of other data. Next, channel device 4 gives circuit control adapter 6-0 the indication of data transmission. Copied data 12 are loaded, byte by byte, and transmitted to the terminal device.
COPYRIGHT: (C)1981,JPO&Japio
JP54159530A 1979-12-07 1979-12-07 Data buffer control method Expired JPS6027427B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54159530A JPS6027427B2 (en) 1979-12-07 1979-12-07 Data buffer control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54159530A JPS6027427B2 (en) 1979-12-07 1979-12-07 Data buffer control method

Publications (2)

Publication Number Publication Date
JPS5682938A true JPS5682938A (en) 1981-07-07
JPS6027427B2 JPS6027427B2 (en) 1985-06-28

Family

ID=15695771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54159530A Expired JPS6027427B2 (en) 1979-12-07 1979-12-07 Data buffer control method

Country Status (1)

Country Link
JP (1) JPS6027427B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5949624A (en) * 1982-09-15 1984-03-22 Omron Tateisi Electronics Co Data transfer device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5949624A (en) * 1982-09-15 1984-03-22 Omron Tateisi Electronics Co Data transfer device

Also Published As

Publication number Publication date
JPS6027427B2 (en) 1985-06-28

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