JPS56789A - Video signal processing circuit - Google Patents
Video signal processing circuitInfo
- Publication number
- JPS56789A JPS56789A JP7613879A JP7613879A JPS56789A JP S56789 A JPS56789 A JP S56789A JP 7613879 A JP7613879 A JP 7613879A JP 7613879 A JP7613879 A JP 7613879A JP S56789 A JPS56789 A JP S56789A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- chroma signal
- output
- circuit
- scanning lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N11/00—Colour television systems
- H04N11/06—Transmission systems characterised by the manner in which the individual colour picture signal components are combined
- H04N11/12—Transmission systems characterised by the manner in which the individual colour picture signal components are combined using simultaneous signals only
- H04N11/14—Transmission systems characterised by the manner in which the individual colour picture signal components are combined using simultaneous signals only in which one signal, modulated in phase and amplitude, conveys colour information and a second signal conveys brightness information, e.g. NTSC-system
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Processing Of Color Television Signals (AREA)
Abstract
PURPOSE:To increase the video quality by perfectly rejecting chroma signal through the rejection of the chroma signal not in common with two horizontal scanning lines with the trap circuit. CONSTITUTION:The composite video signal from the input terminal 5 is divided into two, and one is through the BPF6 passing through the band of chroma signal only. The output is divided into two. One is delayed by 1H period at the delay circuit 7 and it is added with another signal not delayed at the addition circuit 8 to detect the chroma signal not in common in two scanning lines. The detection signal is obtained only for the period corresponding to the part d for difference between two scanning lines. On the other hand, the input from the terminal 5 is added with the output of the delay circuit 7 at the addition circuit 10 and the luminance signal is picked up. But, in this output, the part d chroma signal is left. Then, the remaining chroma signal is rejected for the output of the addition circuit 10 at the trap circuit 11. Thus, since the chroma signal is perfectly rejected, the video quality can be increased.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7613879A JPS56789A (en) | 1979-06-15 | 1979-06-15 | Video signal processing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7613879A JPS56789A (en) | 1979-06-15 | 1979-06-15 | Video signal processing circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56789A true JPS56789A (en) | 1981-01-07 |
Family
ID=13596605
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7613879A Pending JPS56789A (en) | 1979-06-15 | 1979-06-15 | Video signal processing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56789A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4873017A (en) * | 1971-09-06 | 1973-10-02 |
-
1979
- 1979-06-15 JP JP7613879A patent/JPS56789A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4873017A (en) * | 1971-09-06 | 1973-10-02 |
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