JPS5674924A - Method of manufacturing semiconductor element - Google Patents

Method of manufacturing semiconductor element

Info

Publication number
JPS5674924A
JPS5674924A JP15212279A JP15212279A JPS5674924A JP S5674924 A JPS5674924 A JP S5674924A JP 15212279 A JP15212279 A JP 15212279A JP 15212279 A JP15212279 A JP 15212279A JP S5674924 A JPS5674924 A JP S5674924A
Authority
JP
Japan
Prior art keywords
impurity
diffusion
concentration
semiconductor substrate
film thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15212279A
Other languages
Japanese (ja)
Inventor
Shoichi Kitane
Shigeru Honjo
Kenji Azetsubo
Fumio Tobioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15212279A priority Critical patent/JPS5674924A/en
Publication of JPS5674924A publication Critical patent/JPS5674924A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251Diffusion into or out of group IV semiconductors
    • H01L21/2254Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides

Abstract

PURPOSE:To provide a high concentration layer to a substrate having a large diameter effectively by applying a liquid solution including a dopant for a semiconductor substrate to a desired thickness directly, heating it and preparing a diffusion layer. CONSTITUTION:An impure undiluted solution is dropped onto a semiconductor substrate and coats it while rotating. An impurity concentration in a coating film and film thickness for forming are prescribed. Then, when these plates are separately arranged from one another and performed the heat diffusion in a heating furnace, the seat resistance thereof becomes uniform. In this case, the undiluted solution of impurity is controlled to within a range of 16-49.5wt% of the concentration and of 0.7-1.5mu of a film thickness of rotation coating with an alcohol solution including P2O5. As the result of this method, the variation of a sheet resistance is decreased and the diffusion of the impurity can be performed with good controlling.
JP15212279A 1979-11-26 1979-11-26 Method of manufacturing semiconductor element Pending JPS5674924A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15212279A JPS5674924A (en) 1979-11-26 1979-11-26 Method of manufacturing semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15212279A JPS5674924A (en) 1979-11-26 1979-11-26 Method of manufacturing semiconductor element

Publications (1)

Publication Number Publication Date
JPS5674924A true JPS5674924A (en) 1981-06-20

Family

ID=15533535

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15212279A Pending JPS5674924A (en) 1979-11-26 1979-11-26 Method of manufacturing semiconductor element

Country Status (1)

Country Link
JP (1) JPS5674924A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6092611A (en) * 1983-10-26 1985-05-24 Rohm Co Ltd Diffusing method of impurity of semiconductor element
JPS6092610A (en) * 1983-10-26 1985-05-24 Rohm Co Ltd Control method of quantity of boron diffused

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6092611A (en) * 1983-10-26 1985-05-24 Rohm Co Ltd Diffusing method of impurity of semiconductor element
JPS6092610A (en) * 1983-10-26 1985-05-24 Rohm Co Ltd Control method of quantity of boron diffused
JPH0160932B2 (en) * 1983-10-26 1989-12-26 Rohm Kk
JPH0228246B2 (en) * 1983-10-26 1990-06-22 Rohm Kk

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