JPS5668091A - Multiplex transmission load control device - Google Patents
Multiplex transmission load control deviceInfo
- Publication number
- JPS5668091A JPS5668091A JP14409079A JP14409079A JPS5668091A JP S5668091 A JPS5668091 A JP S5668091A JP 14409079 A JP14409079 A JP 14409079A JP 14409079 A JP14409079 A JP 14409079A JP S5668091 A JPS5668091 A JP S5668091A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- address
- output
- clock
- terminal equipment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q9/00—Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
- H04Q9/14—Calling by using pulses
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Time-Division Multiplex Systems (AREA)
- Selective Calling Equipment (AREA)
Abstract
PURPOSE:To prevent extension of terminal equipments and monitor the load, by adding a circuit, which changes the peculiar address by its own output signal, and a circuit, which switches the output of the terminal equipment to the load by the address after change, to the terminal equipment. CONSTITUTION:Relay driving signal (c) is given as clock (d) to counter 2 through delay circuit 1 and is counted and is applied to the address input terminal to change the address of terminal equipment Ba. When receiving a signal agreeing with the address signal which agrees with this changed address, terminal equipment Ba outputs latch signal (b) for relay driving. Signal (c) is output with a short delay after signal (b). The AND output between signal (c) and decoder output (e) is used as clock (f) to drive latch 4, and signal (b) of bus 5 is latched to control the load. After that, clock (d) is delayed by latch clock (f) by 1 to change the address, and another corresponding latches are selected successively. Thus, terminal equipments corresponding to the number of outputs of decorder 3 is substituted with only one.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14409079A JPS5668091A (en) | 1979-11-06 | 1979-11-06 | Multiplex transmission load control device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14409079A JPS5668091A (en) | 1979-11-06 | 1979-11-06 | Multiplex transmission load control device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5668091A true JPS5668091A (en) | 1981-06-08 |
Family
ID=15353981
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14409079A Pending JPS5668091A (en) | 1979-11-06 | 1979-11-06 | Multiplex transmission load control device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5668091A (en) |
-
1979
- 1979-11-06 JP JP14409079A patent/JPS5668091A/en active Pending
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