JPS5668032A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPS5668032A
JPS5668032A JP14417379A JP14417379A JPS5668032A JP S5668032 A JPS5668032 A JP S5668032A JP 14417379 A JP14417379 A JP 14417379A JP 14417379 A JP14417379 A JP 14417379A JP S5668032 A JPS5668032 A JP S5668032A
Authority
JP
Japan
Prior art keywords
contact
potential
low level
level
electric power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14417379A
Other languages
Japanese (ja)
Inventor
Koji Ozawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14417379A priority Critical patent/JPS5668032A/en
Publication of JPS5668032A publication Critical patent/JPS5668032A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
    • H03K19/01735—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals by bootstrapping, i.e. by positive feed-back

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Shift Register Type Memory (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To increase the operation speed of an inverter circuit, making use of bootstrap capacity, by using depletion MISFET for switching. CONSTITUTION:When input signal phi1 is at a low level and phi2 and phi3 are at a high level, contacts N1' and N2' are held at the low level. Next, as signal phi1 rises up to the high level, the potential of contact N1' can be increased nearly up to electric power source potential Vcc since MISFETQ3' is of the depletion type. The potential of contact N2', on the other hand, can be held at earth potential Vss. Once signal phi2 falls down to the low level, MISFETQ2 is cut off and the potential of contact N2 rises, but since the initial voltage of contact N1' is high, contact N2' can be increased up to the electric power source level rapidly. Consequently, the high-speed inverter circuit can be obtained and this can be made hard to be influenced by the threshold voltage and gate voltage of switching MISFET.
JP14417379A 1979-11-07 1979-11-07 Logic circuit Pending JPS5668032A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14417379A JPS5668032A (en) 1979-11-07 1979-11-07 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14417379A JPS5668032A (en) 1979-11-07 1979-11-07 Logic circuit

Publications (1)

Publication Number Publication Date
JPS5668032A true JPS5668032A (en) 1981-06-08

Family

ID=15355895

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14417379A Pending JPS5668032A (en) 1979-11-07 1979-11-07 Logic circuit

Country Status (1)

Country Link
JP (1) JPS5668032A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60124120A (en) * 1983-12-09 1985-07-03 Sony Corp Bootstrap circuit
US4725746A (en) * 1981-10-20 1988-02-16 Kabushiki Kaisha Toshiba MOSFET buffer circuit with an improved bootstrapping circuit
JP2012029306A (en) * 2011-08-23 2012-02-09 Semiconductor Energy Lab Co Ltd Semiconductor device
US8212257B2 (en) 2001-08-10 2012-07-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2013068953A (en) * 2012-09-26 2013-04-18 Semiconductor Energy Lab Co Ltd Semiconductor device
JP2014206741A (en) * 2014-05-20 2014-10-30 株式会社半導体エネルギー研究所 Buffer circuit and semiconductor device

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4725746A (en) * 1981-10-20 1988-02-16 Kabushiki Kaisha Toshiba MOSFET buffer circuit with an improved bootstrapping circuit
JPS60124120A (en) * 1983-12-09 1985-07-03 Sony Corp Bootstrap circuit
US8212257B2 (en) 2001-08-10 2012-07-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8586991B2 (en) 2001-08-10 2013-11-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8841680B2 (en) 2001-08-10 2014-09-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9343485B2 (en) 2001-08-10 2016-05-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9601525B2 (en) 2001-08-10 2017-03-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2012029306A (en) * 2011-08-23 2012-02-09 Semiconductor Energy Lab Co Ltd Semiconductor device
JP2013068953A (en) * 2012-09-26 2013-04-18 Semiconductor Energy Lab Co Ltd Semiconductor device
JP2014206741A (en) * 2014-05-20 2014-10-30 株式会社半導体エネルギー研究所 Buffer circuit and semiconductor device

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