JPS5666072A - Semicondcutor device - Google Patents

Semicondcutor device

Info

Publication number
JPS5666072A
JPS5666072A JP14246279A JP14246279A JPS5666072A JP S5666072 A JPS5666072 A JP S5666072A JP 14246279 A JP14246279 A JP 14246279A JP 14246279 A JP14246279 A JP 14246279A JP S5666072 A JPS5666072 A JP S5666072A
Authority
JP
Japan
Prior art keywords
region
type
substrate
surface concentration
concentration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14246279A
Other languages
Japanese (ja)
Inventor
Yoichi Iga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP14246279A priority Critical patent/JPS5666072A/en
Publication of JPS5666072A publication Critical patent/JPS5666072A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To increase the breakdown voltage on the C-IGFET of the subject semiconductor device without dropping the threshold voltage by a method wherein the numerical values for the surface concentration of a - conduction type semiconductor substrate, the surface concentration of a reverse conduction type inpurity region and the reverse conduction type impurity concentration on a channel region, to be provided in the above impurity region, are prescribed respectively. CONSTITUTION:On the surface of an N type Si substrate 31, having the substrate surface concentration of 1X10<12>-1X10<13>cm<-3>, an SIO2 film 32 is covered and an aperture is opened, ion is injected so as to have the surface concentration of a P type well region 39 of 1X10<14>-1X10<15>cm<-3>, and a P type region 34 is formed. Then the impurities on the region 34 are diffused by performing a heat treatment and a P type well region 39 is obtained. On this region 39, an N type source for an N-channel transistor and drain regions 37 and 38 are formed by diffusion, and also a P type source and drain regions 43 and 44 for a P-channel transistor are provided in the substrate 31 excluding the region 39. After that, a P type impurity ion is injected.
JP14246279A 1979-11-02 1979-11-02 Semicondcutor device Pending JPS5666072A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14246279A JPS5666072A (en) 1979-11-02 1979-11-02 Semicondcutor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14246279A JPS5666072A (en) 1979-11-02 1979-11-02 Semicondcutor device

Publications (1)

Publication Number Publication Date
JPS5666072A true JPS5666072A (en) 1981-06-04

Family

ID=15315871

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14246279A Pending JPS5666072A (en) 1979-11-02 1979-11-02 Semicondcutor device

Country Status (1)

Country Link
JP (1) JPS5666072A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5842265A (en) * 1981-09-07 1983-03-11 Nec Corp Complemental insulated gate field effect semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5842265A (en) * 1981-09-07 1983-03-11 Nec Corp Complemental insulated gate field effect semiconductor device

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