JPS5661662A - Testing method for logic circuit - Google Patents

Testing method for logic circuit

Info

Publication number
JPS5661662A
JPS5661662A JP13744179A JP13744179A JPS5661662A JP S5661662 A JPS5661662 A JP S5661662A JP 13744179 A JP13744179 A JP 13744179A JP 13744179 A JP13744179 A JP 13744179A JP S5661662 A JPS5661662 A JP S5661662A
Authority
JP
Japan
Prior art keywords
logic circuit
logic
test
executed
comprehensive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13744179A
Other languages
Japanese (ja)
Inventor
Chiyoji Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13744179A priority Critical patent/JPS5661662A/en
Publication of JPS5661662A publication Critical patent/JPS5661662A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE: To carry out logic collating which could not be executed with conventional inspection devices making possible not only to test the troubles but also to execute the design debugging of the logic circuit by combining an inspection device and a function simulator.
CONSTITUTION: A hardware logic circuit 3, a test object, is connected to a computer 1 via an inspection adapter 2. The operation test of a comprehensive logic circuit including other logic circuits related with the logic circuit 3 which are required for executing the design debugging of the logic circuit 3 is executed by composing the comprehensive circuit simulating those other logic circuits with the computer 1 using a software.
COPYRIGHT: (C)1981,JPO&Japio
JP13744179A 1979-10-24 1979-10-24 Testing method for logic circuit Pending JPS5661662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13744179A JPS5661662A (en) 1979-10-24 1979-10-24 Testing method for logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13744179A JPS5661662A (en) 1979-10-24 1979-10-24 Testing method for logic circuit

Publications (1)

Publication Number Publication Date
JPS5661662A true JPS5661662A (en) 1981-05-27

Family

ID=15198691

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13744179A Pending JPS5661662A (en) 1979-10-24 1979-10-24 Testing method for logic circuit

Country Status (1)

Country Link
JP (1) JPS5661662A (en)

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