JPS5655075A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5655075A JPS5655075A JP13233679A JP13233679A JPS5655075A JP S5655075 A JPS5655075 A JP S5655075A JP 13233679 A JP13233679 A JP 13233679A JP 13233679 A JP13233679 A JP 13233679A JP S5655075 A JPS5655075 A JP S5655075A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- region
- channel
- type silicon
- boundary
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052710 silicon Inorganic materials 0.000 abstract 4
- 239000010703 silicon Substances 0.000 abstract 4
- 239000000758 substrate Substances 0.000 abstract 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910015365 Au—Si Inorganic materials 0.000 abstract 1
- 239000000969 carrier Substances 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000013078 crystal Substances 0.000 abstract 1
- 230000005684 electric field Effects 0.000 abstract 1
- 230000005496 eutectics Effects 0.000 abstract 1
- 239000011148 porous material Substances 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
PURPOSE:To contrive the enhancement in the performance of a semiconductor device by forming a channel at the portion isolated from the boundary between an island region and an insulating layer, thereby increasing the mobility of carriers in the channel. CONSTITUTION:There is formed an insulating layer 22 which surrounds the N type silicon monocrystalline island region 11, the bottom and side surfaces thereof. This means that P type silicon layer formed in the N type silicon monocrystal is performed in multiple pores and is then oxidized as an SiO2 layer. For example, a high density N<+> type silicon substrate 33 having a specific resistance of 0.01OMEGAcm is formed, and an Au electrode 10 which makes contact ohmically with this through Au-Si eutectic crystal is formed thereat. Further, high density N<+> type source region 44, drain region 55 and P type gate region 66 are formed. When a voltage which is negative with respect to the source 44 is applied to the electrode 10 provided on the substrate 33, a depletion layer 99 is expanded in the bulk of the island 11 from the boundary 88 in the electric field generated between the substrate 33 and the region 11, and a channel is formed between the layer 77 and the layer 99. Accordingly, the layer 99 is expanded in the boundary 88 by the bias voltage applied to the electrode 10, and is formed in the bulk of the island region 11 having high channel mobility.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13233679A JPS5655075A (en) | 1979-10-12 | 1979-10-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13233679A JPS5655075A (en) | 1979-10-12 | 1979-10-12 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5655075A true JPS5655075A (en) | 1981-05-15 |
Family
ID=15078939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13233679A Pending JPS5655075A (en) | 1979-10-12 | 1979-10-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5655075A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5045501A (en) * | 1986-08-25 | 1991-09-03 | Hughes Aircraft Company | Method of forming an integrated circuit structure with multiple common planes |
-
1979
- 1979-10-12 JP JP13233679A patent/JPS5655075A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5045501A (en) * | 1986-08-25 | 1991-09-03 | Hughes Aircraft Company | Method of forming an integrated circuit structure with multiple common planes |
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