JPS5652923A - Analog signal delay circuit - Google Patents

Analog signal delay circuit

Info

Publication number
JPS5652923A
JPS5652923A JP12962679A JP12962679A JPS5652923A JP S5652923 A JPS5652923 A JP S5652923A JP 12962679 A JP12962679 A JP 12962679A JP 12962679 A JP12962679 A JP 12962679A JP S5652923 A JPS5652923 A JP S5652923A
Authority
JP
Japan
Prior art keywords
ram8
converter
analog signal
approximate register
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12962679A
Other languages
Japanese (ja)
Inventor
Kenichiro Oota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Graphtec Corp
Original Assignee
Graphtec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Graphtec Corp filed Critical Graphtec Corp
Priority to JP12962679A priority Critical patent/JPS5652923A/en
Publication of JPS5652923A publication Critical patent/JPS5652923A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks

Landscapes

  • Analogue/Digital Conversion (AREA)
  • Networks Using Active Elements (AREA)

Abstract

PURPOSE:Not only to omit a multiplexer and reduce the number of parts but also to simplify the control, by providing RAM between the sequential approximate register and the D/A converter. CONSTITUTION:When a start command 11 is provided to the sequential approximate register 3, RAM8 becomes a writing mode by a control signal 12, and RAM8 becomes a state that the input and the output are short-circuited in its inside. And the regular A/D conversion is executed by the comparator 1, the sequential approximate register 3 and the D/A converter 2, and its digital value is written in the address designated by the counter 9 of RAM8, by the control signal 12. When the contents of RAM8 are read out by the counter 9 after a prescribed time has passed, a delayed analog signal is received by the terminal 6 through the D/A converter 2 and the simple holding circuit 7.
JP12962679A 1979-10-08 1979-10-08 Analog signal delay circuit Pending JPS5652923A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12962679A JPS5652923A (en) 1979-10-08 1979-10-08 Analog signal delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12962679A JPS5652923A (en) 1979-10-08 1979-10-08 Analog signal delay circuit

Publications (1)

Publication Number Publication Date
JPS5652923A true JPS5652923A (en) 1981-05-12

Family

ID=15014129

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12962679A Pending JPS5652923A (en) 1979-10-08 1979-10-08 Analog signal delay circuit

Country Status (1)

Country Link
JP (1) JPS5652923A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62169511A (en) * 1986-01-22 1987-07-25 Pioneer Electronic Corp Digital delay circuit
JPS63279610A (en) * 1987-05-11 1988-11-16 Advanced Saakitsuto Technol:Kk Digital modulator-demodulator circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62169511A (en) * 1986-01-22 1987-07-25 Pioneer Electronic Corp Digital delay circuit
JPS63279610A (en) * 1987-05-11 1988-11-16 Advanced Saakitsuto Technol:Kk Digital modulator-demodulator circuit

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