JPS5649536A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5649536A
JPS5649536A JP12412579A JP12412579A JPS5649536A JP S5649536 A JPS5649536 A JP S5649536A JP 12412579 A JP12412579 A JP 12412579A JP 12412579 A JP12412579 A JP 12412579A JP S5649536 A JPS5649536 A JP S5649536A
Authority
JP
Japan
Prior art keywords
areas
wafer
lines
test
pair
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12412579A
Other languages
Japanese (ja)
Inventor
Kiyobumi Uchibori
Minoru Honda
Akira Nagai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12412579A priority Critical patent/JPS5649536A/en
Publication of JPS5649536A publication Critical patent/JPS5649536A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Abstract

PURPOSE:To perform the test for operating life time in the form of a wafer with ease by a device wherein a pair of common power source lines are provided at the periphery of a semiconductor wafer including a plurality of IC chip areas formed in line. CONSTITUTION:A plurality of IC chip areas 1 are formed on a semiconductor wafer 7 in the square form with dicing areas 2 therebetween and a pair of power source lines 3 and 4 are continuously formed at two parallel sides of each area 1 extending at right angles with the areas 2. Then, thus arranged areas 1 are formed on the wafer 7 by the predetermined number and a pair of power source terminals 5 and 6 at right angles with the lines 3 and 4 on the peripheral edges of the wafer 7 facing each other. The lines 3 and 4 are respectively connected to the terminals 5 and 6 alternatively. By so doing, all areas 1 can be tested at the same time by applying the source voltage for a test of operating life time only on the paired terminals 5 and 6, so that the test is carried out with high efficiency.
JP12412579A 1979-09-28 1979-09-28 Semiconductor device Pending JPS5649536A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12412579A JPS5649536A (en) 1979-09-28 1979-09-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12412579A JPS5649536A (en) 1979-09-28 1979-09-28 Semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP61219582A Division JPS62169344A (en) 1986-09-19 1986-09-19 Testing method for semiconductor device

Publications (1)

Publication Number Publication Date
JPS5649536A true JPS5649536A (en) 1981-05-06

Family

ID=14877538

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12412579A Pending JPS5649536A (en) 1979-09-28 1979-09-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5649536A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57201042A (en) * 1981-06-05 1982-12-09 Nec Corp Testing method for semiconductor wafer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4975279A (en) * 1972-10-24 1974-07-19
JPS51101473A (en) * 1975-03-04 1976-09-07 Suwa Seikosha Kk HANDOTA ISOCHI

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4975279A (en) * 1972-10-24 1974-07-19
JPS51101473A (en) * 1975-03-04 1976-09-07 Suwa Seikosha Kk HANDOTA ISOCHI

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57201042A (en) * 1981-06-05 1982-12-09 Nec Corp Testing method for semiconductor wafer
JPS6137777B2 (en) * 1981-06-05 1986-08-26 Nippon Electric Co

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