JPS5647830A - Buffer control unit - Google Patents

Buffer control unit

Info

Publication number
JPS5647830A
JPS5647830A JP12454979A JP12454979A JPS5647830A JP S5647830 A JPS5647830 A JP S5647830A JP 12454979 A JP12454979 A JP 12454979A JP 12454979 A JP12454979 A JP 12454979A JP S5647830 A JPS5647830 A JP S5647830A
Authority
JP
Japan
Prior art keywords
transfer
equipment
bytes
buffer
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12454979A
Other languages
Japanese (ja)
Inventor
Kazuo Yasue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12454979A priority Critical patent/JPS5647830A/en
Publication of JPS5647830A publication Critical patent/JPS5647830A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To reduce a transfer time, by providing a buffer between the peripheral control equipment and the peripheral equipment, and transferring a data independently between the buffer and each equipment.
CONSTITUTION: In case it is desired to transfer 18 bytes to the peripheral equipment 32 from the central processing unit 33, the processing unit 33 writes 16 bytes in the first-in first-out (FIFO) memory 2 under control of the control equipment 32. The value of 11 is set to the counter 11, and the flip-flop (FF)121 is set. When transfer of a data of 1 byte has been finished, a pulse is sent out to a signal line 102, the value of the counter 11 is subtracted by 1, and in case of underflow, an output is generated in a signal line 101. As a result, FF121 is reset, FF14 is set, and the remaining 2 bytes are written in the memory 2. After that, FFs 13, 121 are set, and the same operation is executed. Transfer of the final byte is informed by FF13.
COPYRIGHT: (C)1981,JPO&Japio
JP12454979A 1979-09-27 1979-09-27 Buffer control unit Pending JPS5647830A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12454979A JPS5647830A (en) 1979-09-27 1979-09-27 Buffer control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12454979A JPS5647830A (en) 1979-09-27 1979-09-27 Buffer control unit

Publications (1)

Publication Number Publication Date
JPS5647830A true JPS5647830A (en) 1981-04-30

Family

ID=14888220

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12454979A Pending JPS5647830A (en) 1979-09-27 1979-09-27 Buffer control unit

Country Status (1)

Country Link
JP (1) JPS5647830A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01120941U (en) * 1988-02-09 1989-08-16

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4991342A (en) * 1972-12-29 1974-08-31

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4991342A (en) * 1972-12-29 1974-08-31

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01120941U (en) * 1988-02-09 1989-08-16

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