JPS5642490A - Network disconnection system - Google Patents

Network disconnection system

Info

Publication number
JPS5642490A
JPS5642490A JP11753679A JP11753679A JPS5642490A JP S5642490 A JPS5642490 A JP S5642490A JP 11753679 A JP11753679 A JP 11753679A JP 11753679 A JP11753679 A JP 11753679A JP S5642490 A JPS5642490 A JP S5642490A
Authority
JP
Japan
Prior art keywords
call signal
signal pattern
network
disconnected
residual data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11753679A
Other languages
Japanese (ja)
Other versions
JPS6211835B2 (en
Inventor
Shunichi Naito
Yoshiaki Sutani
Hiroshi Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11753679A priority Critical patent/JPS5642490A/en
Publication of JPS5642490A publication Critical patent/JPS5642490A/en
Publication of JPS6211835B2 publication Critical patent/JPS6211835B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:To prevent various disturbance by making it easy to remove residual data when a network is disconnected, by writing a no-call signal pattern in a path memory only for a one-frame period when the network is disconnected as to a time- division switchboard. CONSTITUTION:When the network is disconnected, a no-call signal pattern is generated by variable-transmission-loss insertion and no-call signal pattern generator PADG and then written in path memory SPM, so that not residual data but the no- call signal pattern will be read out with the output of channel counter CTR. After the writing operation, write operation in the write address of the no-call signal pattern is inhibited with a control signal delayed by one frame by delay circuit DL. Therefore, even the decoding of a decoding circuit never generates a DC high-level signal and the switching noise of the network can be reduced.
JP11753679A 1979-09-13 1979-09-13 Network disconnection system Granted JPS5642490A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11753679A JPS5642490A (en) 1979-09-13 1979-09-13 Network disconnection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11753679A JPS5642490A (en) 1979-09-13 1979-09-13 Network disconnection system

Publications (2)

Publication Number Publication Date
JPS5642490A true JPS5642490A (en) 1981-04-20
JPS6211835B2 JPS6211835B2 (en) 1987-03-14

Family

ID=14714217

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11753679A Granted JPS5642490A (en) 1979-09-13 1979-09-13 Network disconnection system

Country Status (1)

Country Link
JP (1) JPS5642490A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0483458A2 (en) * 1990-10-29 1992-05-06 Dsc Communications Corporation Power reduction technique for a time slot interchanger in the subscriber interface

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7332026B2 (en) 2020-07-22 2023-08-23 日本電信電話株式会社 high frequency package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0483458A2 (en) * 1990-10-29 1992-05-06 Dsc Communications Corporation Power reduction technique for a time slot interchanger in the subscriber interface

Also Published As

Publication number Publication date
JPS6211835B2 (en) 1987-03-14

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