JPS5641578A - Block selector of memory unit - Google Patents
Block selector of memory unitInfo
- Publication number
- JPS5641578A JPS5641578A JP11455779A JP11455779A JPS5641578A JP S5641578 A JPS5641578 A JP S5641578A JP 11455779 A JP11455779 A JP 11455779A JP 11455779 A JP11455779 A JP 11455779A JP S5641578 A JPS5641578 A JP S5641578A
- Authority
- JP
- Japan
- Prior art keywords
- lines
- block
- memory
- address
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
Abstract
PURPOSE:To simplify a block selecting circuit while preventing malfunction by using a few address lines from the lowest-order and highest-order ones as memory- unit selection lines and block selection lines. CONSTITUTION:For addition by block selection switches in each memory unit, S2 is a one-bit adder, S3 is a two-bit adder and S4-S7 are three-bit adders. Blocks B1-B8 are selected by comparing circuits C1-C8. The number of address lines A is three and when those three lines are all held at ''0'', the selection state is set. As for four memory units, although memory blocks B1-B8 may be selected in parallel, only one unit is enabled by selecting circuits composed of SW1-SW7, S2-S7 and C2-C8 to operation and in or from one address information is written or read. The high-order three lines are used as block selection lines, the need for an address setting switch is eliminated and setting errors are also eliminated, so that the block selecting circuit can be simplified.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11455779A JPS5641578A (en) | 1979-09-06 | 1979-09-06 | Block selector of memory unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11455779A JPS5641578A (en) | 1979-09-06 | 1979-09-06 | Block selector of memory unit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5641578A true JPS5641578A (en) | 1981-04-18 |
Family
ID=14640779
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11455779A Pending JPS5641578A (en) | 1979-09-06 | 1979-09-06 | Block selector of memory unit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5641578A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4388707A (en) * | 1980-06-30 | 1983-06-14 | Hitachi, Ltd. | Memory selecting system |
JPS5973448A (en) * | 1982-10-18 | 1984-04-25 | Kiyoshi Hajikano | Optical fiber |
-
1979
- 1979-09-06 JP JP11455779A patent/JPS5641578A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4388707A (en) * | 1980-06-30 | 1983-06-14 | Hitachi, Ltd. | Memory selecting system |
JPS5973448A (en) * | 1982-10-18 | 1984-04-25 | Kiyoshi Hajikano | Optical fiber |
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